一种具有延迟校准功能的可编程多相位时钟电路

doi:10.3969/j.issn.1001-2400.2014.06.010

J4 ›› 2014, Vol. 41 ›› Issue (6): 57-64.doi: 10.3969/j.issn.1001-2400.2014.06.010

• Original Articles • Previous Articles Next Articles

Programmable mlti-phase clock circuit with delay calibration

LIU Shubin¹;ZHU Zhangming¹;ZHAO Yang¹;EN Yunfei²;LIU Lianxi¹;YANG Yintang¹

(1. School of Microelectronic, Xidian Univ., Xi'an 710071, China;
2. Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory, Guang Zhou 510610, China)

Received:2013-10-06 Online:2014-12-20 Published:2015-01-19
Contact: LIU Shubin E-mail:shuvin101@126.com

Abstract

Abstract:

Based on the principle of the delay-locked loop (DLL), this paper introduces a programmable multi-phase clock circuit with a delay calibration loop. The proposed circuit offers a clock signal with a precision of 390ps and optimum timing for a variety of CCD signal processors. One cycle of the main clock is divided into 32 parts equally, while timing with a tunable duty cycle is generated by the programmable phase combiner. The increase in delay elements worsens the delay time error between different phases of the output signals, and hence a delay time calibration loop is applied to suppress this effect. In SMIC 0.18μm 3.3V CMOS process, with a 80MHz main clock, the post simulation results show that the proposed circuit generates an output clock with a 2％～98％ duty cycle, a 1.14ps edge to edge jitter and a less than 5ps calibrated delay time error.

Key words: charge couple device, delay locked loop, delay calibration loop, programmable phase combiner

LIU Shubin;ZHU Zhangming;ZHAO Yang;EN Yunfei;LIU Lianxi;YANG Yintang. Programmable mlti-phase clock circuit with delay calibration[J].J4, 2014, 41(6): 57-64.

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Programmable mlti-phase clock circuit with delay calibration

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