Abstract: Reed-Solomon（RS）codes are forward error correct codes which have been widely used in a variety of communication systems and information storages. This paper modifies the extended Euclidean algorithm first. On the basis of the modified algorithm, we have designed the detailed circuit diagram. We use the pipelined recursive structure to solve the key equation of the decoder, which leads to high performance. And we simulate logically the whole RTL level circuit. We design a pipelined fully parallel multiplier to eliminate the speed bottleneck in the conventional decoder. Based on the new RS decode structure, we design and simulate the decoder at the gate level and implement it by the Xilinx VirtexII XC2V1000. Post simulation shows that our decoder performs better in speed and area of the circuit than traditional decoders.

Key words: Reed-Solomon codes, Euclidean algorithm, high speed circuit, FPGA