一种星簇双环片上网络拓扑结构

Abstract

Abstract:

With the feature size of semiconductor process reduced and IP(Intellectual Properties) cores increased, interconnection network architectures on the chip have a great influence on the performance and area of System-on-Chip(SoC) design. Focusing on decreasing node degrees, reducing links and reusing the router node, a regular Network-on-Chip(NoC) architecture, named the Star-Cluster Double-Loop(SCDL(2m)) interconnection network, is proposed. The topology of SCDL(2m) is simple, planar, symmetric and scalable in architecture, and it has 4m nodes. Each node connects three adjacent nodes and four IP cores. The nodes of SCDL(2m) adopt the Johnson coding scheme that can make the design of routing algorithm simple and efficient. The SCDL(2m) is compared with Cluster-Ring and Cluster-Mesh by simulation and analysis, both under a uniform load and under more realistic load assumptions in several network size scenarios. The results show that the SCDL(2m) topology is a good trade-off between performance and cost. It is a better topology for NoC.

Key words: system-on-chip, network-on-chip, network topology, routing algorithms

CLC Number:

TN911.22

LIU You-yao;HAN Jun-gang. Star-cluster double-loop topology for the network-on-chip[J].J4, 2009, 36(6): 1063-1069.

References

［1］Benini L, Micheli G D. Networks on Chip: a New Paradigm for Systems on Chip Design ［C］//Proceedings of Design Automation and Test in Europe Conference and Exhibition. Paris: IEEE, 2002: 418-419.
［2］Horowitz M, Dally W. How Scaling Will Change Processor Architecture［C］//IEEE International Solid-State Circuits Conference. San Francisco: IEEE, 2004: 132-133.
［3］Dally W J, Towles B. Route Packets, Not Wires: On-chip Interconnection Networks ［C］//Proceedi-ngs of Design Automation Conference. Las Vegas: IEEE, 2001: 684-689.
［4］徐阳扬, 周端, 杨银堂, 等. 非对称GALS系统异步接口设计［J］. 西安电子科技大学学报, 2007, 34(2): 294-297.
Xu Yangyang, Zhou Duan, Yang Yintang, et al. Unsymmetrical Interface Design in GALS［J］. Journal of Xidian University, 2007, 34(2): 294-297.
［5］Ye T. On-chip Multiprocessor Communication Network Design and Analysis［D］. California: Stanford University, 2003.
［6］Hu J, Marculescu R. Energy-and Performance-aware Mapping for Regular NoC Architectures［J］. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(4): 551-562.
［7］Salminen E, Kulmala A, Hamalainen T D. Survey of Network-on-Chip Proposals ［R/OL］. ［2008-09-12］. http://www.ocpip.org/socket/whitepapers/.
［8］Salminen E, Kulmala A, Hamalainen T D. On Network-on-chip Comparison［C］//10th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Lübeck: IEEE, 2007: 503-510.
［9］Saneei M, Afzali-Kusha A, Navabi Z. Low-power and Low-latency Cluster Topology for Local Traffic NOCs［C］//Proceedings of IEEE International Symposium on Circuits and Systems. Island of Kos: IEEE, 2006: 1-5.
［10］Jayasimha D N, Zafar B, Hoskote Y. On-Chip Interconnection Networks: Why They are Different and How to Compare Them ［EB/OL］. ［2008-09-12］. blogs. intel.com/research/terascale/.
［11］Duato J, Yalamanchili S, Ni L. Interconnection Networks: an Engineering Approach［M］. Netherland: Elsevier Science, 2003.
［12］Bononi L, Concer N. Simulation and Analysis of Network on Chip Architectures: Ring,Spidergon and 2D Mesh［C］//Proc of the Design, Automation and Test in Europe(DATE). Munich: IEEE, 2006: 54-159.

[1]	XIE Lixia,BAI Yu. Information system business affecting impact evaluation method [J]. Journal of Xidian University, 2021, 48(4): 184-191.
[2]	LIU Lu;ZHOU Xiaofeng;ZHU Zhangming;ZHOU Duan;YANG Yintang. Novel bus arbiter with the two-level arbitration mechanism [J]. Journal of Xidian University, 2017, 44(1): 12-17+105.
[3]	ZANG Mingxiang;WANG Meng;ZHOU Wenhong;CHEN Huicang. Improved shuffled frog-leaping algorithm for low-power network-on-chip mapping [J]. J4, 2015, 42(1): 118-123.
[4]	ZANG Mingxiang;WANG Ting;ZHOU Wenhong. Low energy consumption NoC mapping algorithm based on the modified electromagnetism-like mechanism [J]. J4, 2014, 41(4): 82-86+93.
[5]	LIU Yi;CHEN Bo;YANG Yintang;LIU Gang. High-speed low-power clock network design for NoC [J]. J4, 2013, 40(3): 115-120.
[6]	DENG Zhi;GU Huaxi;YANG Yintang;ZENG Daibing. Artificial bee colony based low-energy consumption high-performance mapping in NoC [J]. J4, 2012, 39(2): 114-119.
[7]	ZHU Bin;ZENG Xiaoping;CHEN Li;LIAO Hongyun;YAN Fang. Research on the adaptive load balancing routing algorithm [J]. J4, 2011, 38(5): 101-107.
[8]	ZHANG Jianxian;ZHOU Duan;YANG Yintang;LAI Rui;GAO Xiang. Low energy consumption mapping algorithm for the network-on-chip [J]. J4, 2011, 38(4): 95-100.
[9]	LIU Yi;YANG Yintang;ZHOU Donghong. Multi-clock router designed for the network-on-chip [J]. J4, 2011, 38(2): 146-150.
[10]	XU Zhan-qi;DING Qiu-ju;CHEN Xiao-hui;DING Zhe. Dynamic traffic grooming algorithm with the adaptively differentiated weight for holding-time-aware services in IP over WDM networks [J]. J4, 2010, 37(5): 801-807.
[11]	TUO Yan-jun;LIU Yun;LIU Yong-jian. Link Load Based Multicast Packet Diffusion Algorithm in the LEO Satellite Constellation System [J]. J4, 2010, 37(2): 380-384.

Star-cluster double-loop topology for the network-on-chip

PDF (PC)

Like

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 11

Metrics

Comments

Recommended 10