考虑热电耦合效应的全芯片温度特性优化方法

Abstract

Abstract:

Based on the fact that convergent results reflecting the feedback between power and temperature can be found by using the available power model and HotSpot software, a method is proposed for full chip temperature optimization. In the model, thermal-electric coupling effects among delay, power and temperature are taken into consideration. Simulations for the AMD Athlon 64 processor in 90-nm technology are given. Results show that the optimized chip temperature characteristics with lower temperature, decreased power and temperature gradients can be achieved.

Key words: delay, power, buffer insertion, thermalelectric coupling

CLC Number:

TN405.97

LENG Peng;DONG Gang;CHAI Chang-chun;YANG Yin-tang. Full chip temperature optimization for considering thermal-electric coupling effects[J].J4, 2009, 36(6): 1053-1058.

References

［1］董刚, 杨银堂, 李跃进. 基于“有效电容”的RLC互连树延时分析［J］. 西安电子科技大学学报, 2004, 31(4): 509-512.
Dong Gang, Yang Yintang, Li Yuejin. Analysis of RLC Interconnect Tree Delay Based on“Effective Capacitance”［J］. Journal of Xidian University, 2004, 31(4): 509-512.
［2］周郭飞, 金德鹏, 曾烈光. 改进的RLC互连延时估算方法［J］. 清华大学学报, 2008, 48(1): 46-50.
Zhou Guofei, Jin Depeng, Zeng Lieguang. Improved Delay Estimation Method for RLC Interconnects［J］. Journal of Tsinghua University, 2008, 48(1): 46-50.
［3］Cong J. An Interconnect-centric Design Flow for Nanometer Technologies［J］. Proceedings of the IEEE, 2001, 89(4): 505-528.
［4］Sylvester D, Keutzer K. A Global Wiring Paradigm for Deep Submicron Design［J］. Computer-Aided Design Integrated Circuits and Systems, 2000, 19(2): 242-252.
［5］Banerjee K, Mehrotra A. A Power-optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs［J］. IEEE Trans on Electron Devices, 2002, 49(11): 2001-2007.
［6］Kapur P, Chandra G, Saraswat K C. Power Estimation in Global Interconnects and Its Reduction Using a Novel Repeater Optimization Methodology［C］//Proceedings of the 39th Annual Design Automation Conference. New York: ACM, 2002: 461-466.
［7］Liu Xun, Peng Yuantao, Papaefthymiou M C. Practical Repeater Insertion for Low Power: What Repeater Library Do We Need?［C］//Proceedings of the 41st Annual Design Automation Conference. New York: ACM, 2004: 30-35.
［8］Wason V, Banerjee K. A Probabilistic Framework for Power-optimal Repeater Insertion in Global Interconnects under Parameter Variations［C］//Proceedings of the 2005 International Symposium on Low Power Electronics and Design. New York: ACM, 2005: 131-136.
［9］Banerjee K, Lin S C, Keshavarzi A, et al. A Selfconsistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management［C］//Electron Devices Meeting, 2003. Washington: IEEE Electronic Devices Society, 2003: 887-890.
［10］He Lei, Liao Weiping, Stan M. System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage［C］//Proceedings of the 41st Annual Design Automation Conference. New York: ACM, 2004: 12-17.
［11］Huang Wei, Humenay E, Skadron K, et al. The Need for a Fullchip and Package Thermal Model for Thermally Optimized IC Designs［C］//Proceeding of Low-Power Electronics Design. New York: ACM, 2005: 245-250.
［12］Ku J C, Ismail Y. Thermal-aware Methodology for Repeater Insertion in Low-Power VLSI Circuits［J］. IEEE Trans on Very Large Scale Integration Systems, 2007, 15(8): 963-970.
［13］Mui M L, Banerjee K, Mehrotra A. Supply and Power Optimization in Leakage-dominant Technologies［J］. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(9): 1362-1371.
［14］HotSpot 4.1. Temperature Modeling Tool［EB/OL］. ［2008-03-24］. http://lava.cs.virginia.edu/HotSpot/.
［15］Link G M, Vijaykrishnan N. Thermal Trends in Emerging Technologies［C］//Proceedings of the 7th International Symposium on Quality Electronic Design. Washington: IEEE Computer Society, 2006: 625-632.
［16］Huang Wei. HotSpot—a Chip and Package Compact Thermal Modeling Methosology for VLSI Design ［D］. Charlottesville: Department of Electrical and Computer Engineering University of Virginia, 2007.
［17］Bakoglu H. Circuits, Interconnections and Packaging for VLSI［M］. New Jersey: Addison-Wesley Pub (Sd), 1990.
［18］Chen Guoqing, Friedman E G. Low-power Repeaters Driving RC and RLC Interconnects with Delay and Bandwidth Constraints［J］. IEEE Trans on Very Large Scale Integration Systems, 2006, 14(2): 161-172.
［19］Su Haihua, Liu F, Devgan A, et al. Full Chip Leakage Estimation Considering Power Supply and Temperature Variations［C］//Proceedings of the 2003 International Symposium on Low Power Electronics and Design. New York: Association for Computing Machinery, 2003: 78-83.
［20］ITRS. International Technology Roadmap for Semiconductors［EB/OL］. ［2008-03-21］. http://www.itrs.net/.

[1]	TIAN Lin,SU Zhijie,FENG Wanmei,CHEN Zhen,TANG Jie,ZHOU Encheng. Trajectory and resource allocation for multi-UAV enabled swipt systems [J]. Journal of Xidian University, 2021, 48(6): 115-122.
[2]	DING Shuo,YANG Haiyan,YANG Xuhai,ZHANG Zhe,ZHAO Kunjuan. Influence of the second-order ionospheric delay on GPS PPP time transfer [J]. Journal of Xidian University, 2021, 48(4): 50-56.
[3]	LI Xinghua,CAI Jueping,LI Xiaolong,WANG Feng,YAN Zhenhua. T-NTRU IoT dynamic access authentication technology [J]. Journal of Xidian University, 2021, 48(3): 188-196.
[4]	TAO Li,TIAN Tong. Si CMOS Ka-band millimeter wave power amplifier [J]. Journal of Xidian University, 2021, 48(2): 190-196.
[5]	HE Bin,SU Hongtao. Study of game strategy between multiple targets and multistatics radars [J]. Journal of Xidian University, 2021, 48(2): 125-132.
[6]	ZHOU Yu,CHEN Zhixiong,ZHUO Zepeng,DU Xiaoni. Survey of results of (n,m)-functions against differential power attack [J]. Journal of Xidian University, 2021, 48(1): 50-60.
[7]	ZHANG Wenzhu,CAO Beibei,YU Jinghua. Multi-user computation offloading approach for mobile edge computing [J]. Journal of Xidian University, 2020, 47(6): 131-138.
[8]	WANG Lu,WANG Leilei. Optimization of the voltage regulators and voltage noise for the power delivery network [J]. Journal of Xidian University, 2020, 47(4): 124-131.
[9]	LIU Daohua,WANG Shasha,YANG Zhipeng,CUI Yushuang. Improved face image classification method based on the local embedding network [J]. Journal of Xidian University, 2020, 47(4): 18-23.
[10]	ZHANG Lu,MU Dejun,HU Wei,TAI Yu. High-level synthesis design flow for power side-channel security [J]. Journal of Xidian University, 2020, 47(4): 64-69.
[11]	ZHANG Gang,HUANG Nanfei,ZHANG Tianqi. Design and performance analysis of the PQMC-NRCDSK [J]. Journal of Xidian University, 2020, 47(1): 1-9.
[12]	XIE Fan,FENG Lifang. Visible light assisted relay communication system and a power allocation scheme [J]. Journal of Xidian University, 2020, 47(1): 95-103.
[13]	GE Qin,XU Bo,TAO Hongqi,WANG Weibo,MA Xiaohua,GUO Fangjin,LIU Yu. W-band 3.4 W/mm GaN power amplifier MMIC [J]. Journal of Xidian University, 2020, 47(1): 24-29.
[14]	ZHANG Mingzhe,WU Haifeng,WEI Shizhe. Design of a broadband high-efficiency power amplifier using the artificial neural network [J]. Journal of Xidian University, 2019, 46(6): 118-124.
[15]	WANG Leilei,WANG Lu. Optimization of the voltage noise induced by the power gating technique [J]. Journal of Xidian University, 2019, 46(5): 48-54.

Full chip temperature optimization for considering thermal-electric coupling effects

PDF (PC)

Like

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Metrics

Comments

Recommended 0