一种用于14位1.28MS/sΣΔADC的数字抽取滤波器设计

doi:10.3969/j.issn.1001-2400.2010.02.024

Abstract

Abstract:

A decimation filter for a 4th-order single-bit single-loop oversampling sigma-delta modulator is designed. Consisting of multi stages, the decimation filter is used to filter the noise in the output signal of the modulator and has a decimation factor of 64. It has a small circuit area and low power dissipation. The filter has been fabricated by the TSMC 0.18μm CMOS process and operates at a voltage of 1.8V. Experimental results show that the output signal of the decimation filter has an SNDR (Signal-to-Noise-and-Distortion-Ratio) of 93.9dB which meets the requirement of the system design. The presented filter has a -6dB pass-band of 640kHz, a power dissipation of 33mW and occupies a die area of about 0.4mm×1.7mm.

Key words: sigma-delta modulator, ADC, decimation filter, FIR filter, CIC filter

YANG Yin-tang,LI Di,SHI Li-chun. Decimation filter design for 14-bit 1.28MS/s sigma-delta ADC[J].J4, 2010, 37(2): 315-319.

References

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Decimation filter design for 14-bit 1.28MS/s sigma-delta ADC

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