一种精简的高速率功率MOS驱动器

doi:10.3969/j.issn.1001-2400.2012.02.028

J4 ›› 2012, Vol. 39 ›› Issue (2): 168-174.doi: 10.3969/j.issn.1001-2400.2012.02.028

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High-speed gate driver with a simple structure for power MOSFET

HE Huisen^1,2;LAI Xinquan^1,2;XU Wendan³;ZHAO Yongrui^1,2;TIAN Lei⁴;DU Hanxiao^1,2

(1. Research Inst. of Electronic CAD, Xidian Univ., Xi'an 710071， China;
2. Ministry of Education Key Lab. of High-Speed Circuit Design and EMC, Xidian Univ., Xi'an 710071， China;
3. Library, Xi'an Aerotechnical Collage, Xi'an 710071， China;
4. School of Electronic Eng., Xi'an Univ. of Posts ＆ Telecommunications, Xi'an 710121， China)

Received:2011-03-17 Online:2012-04-20 Published:2012-05-21
Contact: HE Huisen E-mail:xqlai@mail.xidian.edu.cn

Abstract

Abstract:

A novel gate driver with a low transmission delay and ultra-low dead-time is proposed for driving power MOSFET. It controls the charge time and discharge time of the gate capacitor for minimizing dead-time, and no extra current bias and logic circuits are required, so it can simplify the driver circuit and reduce the noise in the current bias. Based on the 0.4 μm BCD process, the simulation is done in the Cadence environment, with good performance observed where the dead-time is below 10ns and the transmission delay is below 70ns. Then a Power Factor Correction (PFC) IC which utilizes this gate driver is tested for validation, and the test results indicate that the t_rise and t_{f_all} are 90ns and 55ns respectively that the power factor is 0.995, and that the Total Harmonic Distortion (THD) is as low as 6.5％.

Key words: driver circuits, power MOSFET, power factor correction, BCD process, dead time

CLC Number:

TN386

HE Huisen;LAI Xinquan;XU Wendan;ZHAO Yongrui;TIAN Lei;DU Hanxiao. High-speed gate driver with a simple structure for power MOSFET[J].J4, 2012, 39(2): 168-174.

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[1]	LIU Lianxi;YANG Yintang;ZHU Zhangming. Design of a high output power step down DC/DC converter with the peak current control mode [J]. J4, 2011, 38(2): 135-140.
[2]	SHI Lingfeng;WANG Qingbin;XU Wendan;MIAO Zihui. Design of the low-power MOSFET driver circuit for APFC [J]. J4, 2011, 38(1): 54-58+65.
[3]	LI Ya-ni;YANG Yin-tang;ZHU Zhang-ming. Double-loop control one cycle PFC converter high-level model and its circuit realization [J]. J4, 2010, 37(4): 608-612.

High-speed gate driver with a simple structure for power MOSFET

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