J4 ›› 2011, Vol. 38 ›› Issue (1): 54-58+65.doi: 10.3969/j.issn.1001-2400.2011.01.009

• Original Articles • Previous Articles     Next Articles

Design of the low-power MOSFET driver circuit for APFC

SHI Lingfeng1,2;WANG Qingbin1,2;XU Wendan1,2;MIAO Zihui3   

  1. (1. Ministry of Education Key Lab. of High-Speed Circuit Design and EMC, Xidian Univ., Xi'an  710071, China;
    2. Research Inst. of Circuit Design, Xidian Univ., Xi'an  710071, China;
    3. Shanghai Institute of Satellite Engineering, Shanghai  200240, China)
  • Received:2010-03-24 Online:2011-02-20 Published:2011-04-08
  • Contact: SHI Lingfeng E-mail:lfshi@mail.xidian.edu.cn

Abstract:

AA drive circuit for driving an external power MOSFET is designed for active power factor correction (APFC), which consists of a level-shift circuit and a single totem-pole output stage. The level-shift circuit adopts the current mirror structure so that it can reduce the power dissipation by adjusting the bias current. The dead time in the single totem-pole output stage can also decrease the power dissipation. Clamping the control signal VGS for the high voltage PMOS between 6V and 11V not only makes low consumption but also saves the layout area. Based on the 0.4μm BCD process, simulation results show  that the better circuit power is 7.34mW and that the layout area can be saved by 15% when VDD is 14V and switch frequency is 75kHz.

Key words: active power factor correction, low-power, level-shift, power MOSFET