J4 ›› 2013, Vol. 40 ›› Issue (6): 58-61.doi: 10.3969/j.issn.1001-2400.2013.06.010

• Original Articles • Previous Articles     Next Articles

Development and realization of P-channel VDMOS

PU Shi;HAO Yue   

  1. (Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials  and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2012-08-02 Online:2013-12-20 Published:2014-01-10
  • Contact: PU Shi E-mail:victor.pu1981@gmail.com

Abstract:

The relationship among the breakdown voltage, the epitaxial layer parameter and the on-state resistance of P-channel VDMOS has been analyzed. By using Silvaco, the structure, physical parameters and electrical properties of the P-channel VDMOS cell are simulated and optimized. Also, a terminal structure has been designed for this device. An 80V/14A P-channel power VDMOS has been successfully designed and manufactured totally based on the process of domestic fab, with both of its static and dynamic characteristics reaching the design criterion during the tests.

Key words: P-channel VDMOS, optimized epitaxial layer, junction termination technique

CLC Number: 

  • TN432