J4 ›› 2013, Vol. 40 ›› Issue (6): 6-12.doi: 10.3969/j.issn.1001-2400.2013.06.002

• Original Articles • Previous Articles     Next Articles

Low complexity decoding algorithm for LDPC codes and design of key circuits

MA Kexiang;LIU Yi;HU Jianhua;SUN Jicheng;ZHANG Hailin   

  1. (State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an  710071, China)
  • Received:2012-09-07 Online:2013-12-20 Published:2014-01-10
  • Contact: MA Kexiang E-mail:kxma@mail.xidian.edu.cn

Abstract:

Parallel Weighted Bit Flipping(PWBF) can achieve a good decoding performance. However, it is hard for the hardware design and implementation because of the high complexity of its bit-chosen mechanism. By improving the bit-chosen mechanism in PWBF, a low-complexity decoding algorithm is proposed in this paper. Especially, in each iteration step of decoding, after the metric value of every bit is updated, several bits with the largest metric values are flipped. Furthermore, the optimized circuits with low complexity are provided for the critical modules of the proposed algorithm. Compared with the PWBF algorithm, the complexity of LDPC decoders is greatly decreased by use of the proposed algorithm and the optimized circuits.

Key words: LDPC code, WBF, parallel binary tree, choose network