Abstract: Based on the data-flow model and hardware reconfigurable technology, a polymorphic reconfigurable many-core processor architecture is presented for image processing. It is a scalable hierarchically organized parallel architecture, which is capable of supporting a dynamic mixture of multiple parallel computing models, and overcomes the inefficiency of traditional data-flow implementation by using distributed shared memory and neighbor interconnect architecture with hardware handshaking. From the beginning of the architecture design, based on the VC++, the integrated simulation platform (ISE) is developed for verifying the architecture and the performance of the instruction set. In addition, we also implement the proposed architecture on the FPGA. Experimental results show that the architecture can be used in many image processing applications, and achieve the throughput close to that of the ASIC and the performance better than that of the GPU.

Key words: polymorphic reconfigurable architecture, data-flow, many-core, parallel computin