一种CNFET的多位三值比较器设计

doi:10.3969/j.issn.1001-2400.2016.01.025

Abstract

Abstract:

As the ternary comparator faces problems of slow speed and high power consumption, this paper proposes a scheme for the magnitude ternary comparator of CNFET, which is researching on theory of multi-valued logic circuit and the structure of comparator circuit. First, the ternary decode signal is propagated to the comparator, then the encoder circuit encodes the results of comparison, and finally the magnitude ternary comparator is made up of all kinds of modules. The magnitude comparator is simulated by software, which demonstrates that it has a correct logic function, fast speed and low power consumption characteristics.

Key words: multi-valued logic, CNFET, low power consumption, comparator, codec

TANG Weitong;WANG Pengjun;WANG Qian. Design of the magnitude ternary comparator of CNFET[J].J4, 2016, 43(1): 139-143+156.

References

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Design of the magnitude ternary comparator of CNFET

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