应用于低压锁相环的高性能可编程电荷泵

doi:10.3969/j.issn.1001-2400.2016.02.032

Abstract

Abstract:

This paper proposes a charge pump with a programmable output current for low voltage phase-locked loops (PLLs). It consists of two sub-units both of which leverage replica bias and feedback control techniques to achieve perfect match between charging and discharging currents. With the help of the current summing structure, the output current variation in each sub charge pump can be compensated by the other. Thus, their sum current remains relatively constant in a wide output voltage range. The charge pump can be programmed to output a 50μA～1.55mA current, with a 50μA minimum step. It is designed in a 0.13μm CMOS process and the post-layout simulation demonstrates the total current mismatch and variation rates are limited in 0.15％ and 5％, over the output voltage range of 0.1～1.05V. Such precise matching greatly suppresses the reference spur and static phase error, and the good current constancy is favorable for dynamic design. Both features render our design suitable for low voltage PLLs.

Key words: charge pump, output current matching, programmable output current, phase-locked loop

LIANG Liang;ZHU Zhangming;YANG Yintang. High-performance programmable charge pump for low voltage PLLs[J].Journal of Xidian University, 2016, 43(2): 186-192.

References

［1］ LEVANTINO S, MARZIN G, SAMORI C, et al. A Wideband Fractional-N PLL with Suppressed Charge-pump Noise and Automatic Loop Filter Calibration ［J］. IEEE Journal of Solid-State Circuits, 2013, 48(10): 2419-2429.
［2］ GAIED D, HEGAZI E. Charge-pump Folded Noise Cancelation in Fractional-N Phase-Locked Loop ［J］. IEEE Transactions on Circuits and System II: Express Briefs, 2014, 61(6): 378-382.
［3］ MOON J W, CHOI K CI, CHOI W Y. A 0.4V, 90 ～ 350-MHz PLL with an Active Loop-filter Charge Pump ［J］. IEEE Transactions on Circuits and System II: Express Briefs, 2014, 61(5): 319-323.
［4］ YOSHIMURA T, IWADE S, MAKINO H, et al. Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-locked Loop ［J］. IEEE Transactions on Circuits and System I: Regular Papers, 2013, 60(4): 896-907.
［5］冯焱, 罗阳, 陈贵灿. 具有稳定环路带宽功能的多模分数频率综合器［J］. 西安电子科技大学学报, 2013, 40(5): 119-123.
FENG Yan, LUO Yang, CHEN Guican. Multi-mode Fractional-N Frequency Synthesizer with a stabilized loop bandwidth ［J］. Journal of Xidian University, 2013, 40(5): 119-123.
［6］ KAMAL N, AL-SARAWI S F, ABBOTT D. Reference Spur Suppression Technique using Ratioed Current Charge Pump ［J］. Electronics Letters, 2013, 49(12): 746-747.
［7］ ZHOU J Z, WANG Z G. A High-performance CMOS Charge-pump for Phase-locked Loops ［C］//Proceedings of the International Conference on Microwave and Millimeter Wave Technology: 2. Piscataway: IEEE, 2008: 839-842.
［8］ JORAM N, WOLF R, ELLINGER F. High Swing PLL Charge Pump with Current Mismatch Reduction ［J］. Electronics Letters, 2014, 50(9): 661-663.
［9］ YAN H, QIN P, CHEN D P. A New Phase Noise Cancelling Technique for Fractional-N PLL ［C］//IEEE International Conference on Solid-State and Integrated Circuit Technology. Piscataway: IEEE, 2014: 1-3.
［10］ HATI M K, BHATTACHARY T K. A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 0.13-μm CMOS ［C］//International Conference on VLSI Systems, Architecture, Technology and Applications. Piscataway: IEEE, 2015: 1-6.
［11］ TSITUORAS A, PLESSAS F, BIRBAS M, et al. A 1V CMOS Programmable Accurate Charge Pump With Wide Output Voltage Range ［J］. Microelectronics Journal, 2011, 42(9): 1082-1089.

[1]	JING Xin;ZHUANG Yiqi;TANG Hualian;ZHANG LI;DU Yongqian. Novel dual-channel MOS bootstrapped switch circuit [J]. J4, 2014, 41(3): 138-144.
[2]	ZHANG Xueping;ZHOU Wei;LI Zhiqi;MIAO Miao. Phase quantum and its application between periodic signals [J]. J4, 2012, 39(5): 181-185.
[3]	NING Xiaoling;LIU Zhong;LUO Yasong;GONG Li;FU Xuezhi. Improved super-exponential iteration blind equalization algorithm for carrier phase recovery in underwater acoustic channels [J]. J4, 2012, 39(1): 151-156.
[4]	LIU Hong-yan1;LUAN Xiao-feng1;LIU Chuan-jun2. Design of the low-noise high-speed differential charge-pump phase-lock loop [J]. J4, 2009, 36(3): 557-562.

High-performance programmable charge pump for low voltage PLLs

PDF (PC)

Like

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 4

Metrics

Comments

Recommended 10