超低时延免迭代CORDIC算法

doi:10.3969/j.issn.1001-2400.2017.04.028

Abstract

Abstract:

The pipeline structure Coordinate Rotation Digital Computer (CORDIC) algorithm improves its precision by increasing the stages of iterations, which leads to a large delay, excessive consumption of hardware and limits its applications.The omit-iteration CORDIC algorithm is proposed to solve this problem by using the methods of binary to bipolar recoding, folding angle domain, merging iteration and optimizing the lookup table. Simulation results show that this method needs only two clock cycles to get the output and also makes improvement on the hardware consumption and its precision, especially having privilege to the application on high speed and real-time occasions compared with other realization of the CORDIC algorithm.

Key words: coordinate rotation digital computer, omit-iteration, binary to bipolar recoding, field-programmable gate array, digital signal processing

YAO Yafeng;FENG Zhongxiu;CHEN Zhao. Ultra-low latency and omit-iteration CORDIC algorithm[J].Journal of Xidian University, 2017, 44(4): 162-166.

References

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Ultra-low latency and omit-iteration CORDIC algorithm

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