Abstract:

Placement is one of the most time-consuming steps of the Field Programmable Gate Array (FPGA) computer aided design flow. In order to accelerate the placement step, a novel approach to FPGA placement is proposed. First, circuit logic blocks choose to use the lowest cost physical resources, and it is allowed that multiple logic blocks share the same resource. Second, the logic blocks using the overused physical resources are re-placed iteratively; the cost of the overused resources is gradually increased, thus eliminating the overuse of the physical resources progressively. Finally, the low-temperature simulated annealing algorithm is applied to optimize the placement result. Experimental results show that the proposed approach reduces the placement runtime by 52% compared with the state-of-the art placement tool, with a reduction of critical path delay and total wirelength by 4.8% and 1.9%, respectively. The proposed approach significantly accelerates the FPGA placement and hence shortens the compile-debug cycle of circuits, which is helpful to improving the efficiency of the developers.

Key words: field programmable gate array, computer aided design, placement, circuit design