Abstract: A new adder design is proposed. Combining CLA and asynchronous self-timed techniques,the adder introduces the hybrid handshake protocol and distributes the carry-generating path with the probabilities of the carry chains. It can speed up the asynchronous adder while keeping a low power and area cost. The adder implements the 0.18μm technique of SMIC. Simulation result shows that the 32-bit asynchronous parallel adder achieves the average delay of 0.880932ns. Its speed is 7.33 times faster than the synchronous ripple adder, 1.364 times faster than the asynchronous ripple adder, and 1.123 times faster than the asynchronous carry-select adder. And its area and power cost are less than those of the asynchronous carry-select adder.

Key words: asynchronous, parallel, carry-look-ahead, adder, self-timed