Abstract: Based on the cost of hardware implementation and the precision of estimation, a new block-matching algorithm named the Hierarchical Quasi-Full Search Algorithm(HQFSA) is proposed. HQFSA can be easily realized by hardware. A parallel architecture as well as a pipelining architecture is proposed based on one-dimentional array processor with sequential inputs and processing with 100 percent efficiency. The HQFSA combines the main idea in the full search algorithm with that in the hierarchical block matching algorithm. The hardware cost of HQFSA is a quarter that of the full search algorithm. The clock frequency is reduced as a result of the parallel architecture. The experimental results show that the PSNR of HQFSA is comparable to that of the full search algorithm and better than that of the hierarchical block matching algorithm and other fast matching algorithms. We have also proposed an data memory scheme for reducing the cost based on the recommendation H.263. We have already realized this algorithm using FPGA.

Key words: motion estimation and compensation, hierarchical quasi full search algorithm, parallel processing, pipelining architecutre, hardware architecture