Abstract: The design of a 32×32-b multiplier by using a modified Carry-Select Adder, a 4-2 compressor, and a 4 Booth encoder is presented. The description of the multiplier in Verilog is simulated on Active-HDL 5.1, which shows that the design has advantages over some others in layout and frequency.

Key words: CSA, multiplier, Booth encoding, Carry-select