高吞吐率JPEG2000编码器VLSI设计

doi:10.19665/j.issn1001-2400.2022.04.020

Abstract

Abstract:

Aiming at the pressure of storage and transmission bandwidth massive image data in practical applications,a high throughput image compression encoder compatible with processing 8~16 bits grayscale images is designed,and the corresponding VLSI architecture is given.By analyzing the characteristics of the 16-bit gray image pixel value,and the difference between Discrete Wavelet Transform(DWT) and Optimized Truncated Embedded Module(EBCOT) with the hardware implementation of the JPEG2000 compression encoder in the processing time,the optimal parallel-series-parallel structure is proposed,and the architecture is designed with high 8-bit and low 8-bit processing,which can be processed independently or together.This architecture increases the flexibility of the encoder and greatly improves the throughput of the compression encoder.Finally,the encoder is implemented on Xilinx XC7K480T.The highest operating frequency of the encoder is 147.734 MHz,and the maximum throughput rate of the 8-bit grayscale image is 169.55 MB/s.The maximum throughput of the 16-bit grayscale image is 266.87 MB/s.Compared with existing similar encoders,the throughput is increased by more than 40%.In practical engineering applications,the encoder has not only a high reliability and good flexibility,but also a strong scalability.By controlling the parallelism,it can realize high magnification,high quality and fast compression of images with different resolutions,which is of important practical value.

Key words: image compression, very large scale integration, parallel processing, throughput

CLC Number:

TN47

WU Changkun,ZHANG Wei,HAO Yazhe. Design of a hardware compression encoder with a high throughput[J].Journal of Xidian University, 2022, 49(4): 176-183.

Figures/Tables 10

References 21

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10	9	8	7	6	5	4	3	2	1	输出(二进制)
*	*	*	*	*	*	*	*	*	1	0000000001
*	*	*	*	*	*	*	*	1	0	0000000010
*	*	*	*	*	*	*	1	0	0	0000000100
*	*	*	*	*	*	1	0	0	0	0000001000
*	*	*	*	*	1	0	0	0	0	0000010000
*	*	*	*	1	0	0	0	0	0	0000100000
*	*	*	1	0	0	0	0	0	0	0001000000
*	*	1	0	0	0	0	0	0	0	0010000000
*	1	0	0	0	0	0	0	0	0	0100000000
1	0	0	0	0	0	0	0	0	0	1000000000
0	0	0	0	0	0	0	0	0	0	0000000000

图像(8 bit)	压缩比5∶1			压缩比50∶1
图像(8 bit)	消耗周期数	PSNR值/dB	吞吐率/ (MB·s^-1)	消耗周期数	PSNR值/dB	吞吐率/ (MB·s^-1)
图6(a)(原始高8位)	1 117 971	66.65	264.29	1 110 554	46.95	266.05
图6(a)(原始低8位)	1 032 507	44.74	264.29	1 009 620	34.64	266.05
图6(b)(原始高8位)	1 120 280	66.23	263.74	1 112 874	47.29	265.50
图6(b)(原始低8位)	1 051 483	44.56	263.74	1 025 356	33.91	265.50
图6(c)(原始高8位)	1 116 449	66.16	264.65	1 109 133	47.44	266.40
图6(c)(原始低8位)	1 072 007	41.31	264.65	1 045 856	31.99	266.40
图6(d)(原始高8位)	1 114 281	66.48	265.16	1 107 156	47.19	266.87
图6(d)(原始低8位)	1 092 844	42.21	265.16	1 066 813	32.83	266.87

图像(16 bit)	压缩比5∶1	压缩比50∶1
图6(a)	58.11	36.23
图6(b)	58.29	36.03
图6(c)	56.15	36.37
图6(d)	57.04	35.20

像素差值	5∶1高位图	5∶1低位图	50∶1高位图	50∶1低位图
0	99.220	64.13	97.70	53.86
1	0.610	19.75	0.70	7.60
2	0.130	8.24	0.29	6.57
3	0.030	3.25	0.20	5.33
4	0.005	1.53	0.16	4.22
5	0.005	0.87	0.13	3.30
其他	0	2.23	0.82	25.69

架构来源	像素位宽/ bit	压缩算法	实现方式	硬件平台	最大时钟频率/MHz	吞吐率/ (MB·s^-1)	EPI/mJ
文献[5]	8	JPEG	FPGA	Xilinx XC6SLX75	148.500	98.50	5.030
文献[6]	8	JPEG XR	FPGA	Altera EP2S130F1020I4	100.000	41.70
文献[7]	8	JPEG XR	FPGA	Altera EP3C25	52.000	16.00	11.375
文献[8]	8	JPEG2000	ASIC	ADV212		65.00	5.380
文献[10]	8	JPEG2000	FPGA	Xilinx 6VSX475T	147.018	120.00
文中	8	JPEG2000	FPGA	Xilinx 6VSX475T	133.895	154.03	5.540
文献[11]	8	JPEG2000	FPGA	Xilinx XC7VX485T	53.968	16.20	7.245
文中	8	JPEG2000	FPGA	Xilinx XC7VX485T Xilinx XC7K480T	147.734	169.55	4.430 4.390
文中	16	JPEG2000	FPGA	Xilinx XC7K480T	147.734	266.87	3.580

Design of a hardware compression encoder with a high throughput

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References 21

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并行度	查找表	BRAM	DSP	最大时钟频率/MHz
1	20 905	29	17	147.734
2	37 319	51	20	147.734
4	70 916	95	26	147.734
8	138 266	183	38	147.734
12	206 528	271	50	147.734

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