256MHz采样71dB动态范围连续时间ΣΔADC设计

doi:10.3969/j.issn.1001-2400.2015.01.002

J4 ›› 2015, Vol. 42 ›› Issue (1): 10-15.doi: 10.3969/j.issn.1001-2400.2015.01.002

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Continuous time ΣΔADC design with 256MHz sampling and 71dB DR

YANG Yintang¹;YUAN Jun¹;ZHANG Zhaofeng²

(1. Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071, China;
2. Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201203, China)

Received:2013-10-27 Online:2015-02-20 Published:2015-04-14
Contact: YANG Yintang E-mail:ytyang@xidian.edu.cn

Abstract

Abstract:

A wide bandwidth continuous time ΣΔADC is widely used in the wireless communication field. A ΣΔADC with the 3 order 4bit modulator is designed with the 256MHz sampling frequency. In order to reduce the clock jitter, the nonreturn-to-zero (NRZ) DAC feedback pulse is used. And the loop asynchronous problem is improved by introducing a half of clock cycle delay. Also how to reduce the effect of the DAC mismatch is discussed. A low voltage, low power, and high speed operational amplifier is designed with feedforward compensation technology. Finally, based on the 0.13μm technology, the SNDR is 62.5dB and DR is 71dB with a 1.2V supply.

Key words: analog to digital converter, continuous time, sigma delta analog to digital converter

CLC Number:

YANG Yintang;YUAN Jun;ZHANG Zhaofeng. Continuous time ΣΔADC design with 256MHz sampling and 71dB DR[J].J4, 2015, 42(1): 10-15.

References

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[1]	WANG Xiaofei;HAO Yue. Design of double sample 1.2V 7bit 125MS/s pipelined ADC [J]. Journal of Xidian University, 2016, 43(4): 23-28.
[2]	WANG Yajun;LI Ming. Novel method for compensation of timing mismatch in time-interleaved ADC [J]. J4, 2012, 39(2): 101-107.
[3]	WANG Chao;ZHU Jian-ming;MA Jian-feng. Analysis of the availability of component-based software systems [J]. J4, 2004, 31(5): 781-784.

Continuous time ΣΔADC design with 256MHz sampling and 71dB DR

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