一种双采样1.2V 7位125MS/s流水线ADC的设计

doi:10.3969/j.issn.1001-2400.2016.04.005

Abstract

Abstract:

A 7bit 125MS/s double sample pipelined ADC which can achieve a low power and a high performance for the SoC system is presented. The presented ADC with op-amp sharing between two channels and a new timing scheme can not only eliminate sampling timing skew, but also has a low power and a small area. Test results show that the ADC designed in a 0.13μm CMOS process achieves a maximum SNDR of 43.38dB, and that ENOB is 6.8bits. The ADC consumes 10.8mW at 125MS/s under a 1.2V supply voltage.

Key words: double sample, op-amp sharing, time-interleaved, pipelined analog to digital converter

WANG Xiaofei;HAO Yue. Design of double sample 1.2V 7bit 125MS/s pipelined ADC[J].Journal of Xidian University, 2016, 43(4): 23-28.

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Design of double sample 1.2V 7bit 125MS/s pipelined ADC

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