低功耗时间交织12位500MS/s电荷域ADC

doi:10.3969/j.issn.1001-2400.2017.06.020

Abstract

Abstract:

A feed-forward common-mode(CM) charge compensation circuit and a foreground calibration technique for the high speed charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented to solve the problem that the precision of CD pipelined ADCs is restricted by the variation of the input CM charge and the offset error. The proposed compensation circuit and the calibration technique can compensate the CM charge and errors caused by the variation of the input CM charge and offset respectively. Based on the feed-forward CM charge compensation circuit and the offset error foreground calibration technique, a 12bit 500MS／s time-interleaved CD pipelined ADC is designed and realized in a 1P6M 018μm CMOS process. The ADC achieves the spurious free dynamic range (SFDR) of 775dB and the signal-to-noise-and-distortion ratio (SNDR) of 627dBFS for a 199MHz input at a full sampling rate. The variation of signal-to-noise ratio is less than 3dB for the input CM voltage in the 0 to 12V range. The power consumption of the prototype ADC is only 220mW at 18V supply and occupies the active die area of 624mm².

Key words: pipelined analog-to-digital converter, charge domain, time-interleaved, feed-forward compensation, offset calibration

CHEN Zhenhai;WEI Jinghe;SU Xiaobo;ZOU Jiaxuan;ZHANG Hong;YU Zongguang. Low power time-interleaved 12-bit 500MS／s charge-domain ADC[J].Journal of Xidian University, 2017, 44(6): 109-115+137.

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[1]	CHEN Zhenhai, WEI Jinghe, YU Zongguang, SU Xiaobo, XUE Yan, ZHANG Hong. High precision common mode charge error fore-ground calibration circuit for the charge-domain ADC [J]. Journal of Xidian University, 2018, 45(6): 137-143+149.
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[3]	HUANG Songren;CHEN Zhenhai;ZHANG Hong;LI Xue;QIAN Hongwen;YU Zongguang. 1.5bit substage circuit for charge domain pipelined ADCs [J]. Journal of Xidian University, 2016, 43(6): 170-175.
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[7]	YANG Xiao;CHEN Gui-can;CHENG Jun;ZHANG Hong. Novel two-channel time-interleaved high-order ΣΔ modulator [J]. J4, 2009, 36(2): 359-365.

Low power time-interleaved 12-bit 500MS／s charge-domain ADC

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