Abstract: We present a bit plane-parallel architecture for a modified SPIHT algorithm using depth-first search bit stream processing which is suitable for VLSI implementation. In the architecture, the coding information of each bit plane can be obtained simultaneously. that is, the ancestor-descendant relationship between coefficients of the tree stucture can be calculated by logical operators. Then, the corresponding VLSI architecture for implementing the formulated requirements is presented. Compared with other architectures, this has advantages of high parallelism, no intermediate buffer and the ability to scan with error resilience as a single tree. The experimental results show that the proposed architecture reduces the processing time greatly compared with others. The quality of images can satisfy most application fields.

Key words: image compression, SPIHT, bit plane-parallel, VLSI architecture