一种高效的H.264 CABAC解码器的VLSI结构

Abstract

Abstract:

A hardware implementation of the Context-based Adaptive Binary Arithmetic Coding(CABAC) decoder for H.264/AVC is presented. Based on the full use of the parallel architecture, an efficient solution for VLSI implementation is described. By developing the two-level finite state machines to control the decoding process and adopting the memory clear schedule to solve the problem of coefficients storage being time-consuming, the complexity of CABAC-decoder implementation is reduced, and the speed is increased to generate one bit within one or two cycles. Simulation results testify that our design can meet the needs of decoding the H. 264/AVC main profile CIF bit stream at 30fps in real time.

Key words: H.264/AVC, CABAC-decoder, VLSI, finite state machine

CLC Number:

TN919.81

SHI Ying-bo;LI Yun-song;ZHANG Jian-long. An efficient VLSI architecture of the CABAC decoder in H.264[J].J4, 2006, 33(6): 844-848.

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An efficient VLSI architecture of the CABAC decoder in H.264

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