Abstract: There are several TAM architectures with each IP core connected with only one TAM. In this paper, the switching TAM architecture is presented in which each IP core can be connected with one TAM directly or more TAMs with a switching circuit. So some IP cores can be tested by several TAMs, which will reduce the idle time and test time effectively. By 0-1 programming, which is restricted in some given conditions, each IP core is allocated to a TAM, and then a heuristic search arithmetic is used to pick out some appropriate IP cores which could be tested by several TAMs. The test time of our approach on ITC2002 benchmark circuits is less than that of some other approaches.

Key words: test access mechanism, test scheduling, test time, 0-1 programming