全数字接收机中一种低功耗插值滤波器结构及其VLSI实现

doi:10.3969/j.issn.1001-2400.2010.02.025

Abstract

Abstract:

The interpolation filter is the key technology for realizing bit synchronization in all-digital receiver. This paper introduces the structure of the interpolation filter, which is suitable for VLSI. A new structure based on the Farrow structure of Lagrange is proposed, which can be used to improve the operational rate of the filter by pipelining and Parallel processing technology. A comparison in operational rate, hardware complexity and the energy consumption between improved structure and original structure is made. It has been realized by using FPGA.Simulation and experiment show that the structure has a faster operational rate and lower power.

Key words: all digital receiver, VLSI, interpolation filter, Farrow structure

DENG Jun. Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver[J].J4, 2010, 37(2): 320-325.

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Structure of the low-power interpolation filter and its VLSI implementation for all-digital receiver

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