一种R-C-R组合式12位逐次逼近A／D转换器

doi:10.3969/j.issn.1001-2400.2010.05.023

J4 ›› 2010, Vol. 37 ›› Issue (5): 904-910.doi: 10.3969/j.issn.1001-2400.2010.05.023

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12-bit SAR A／D converter with an R-C-R hybrid architecture

TONG Xing-yuan¹;CHEN Shan²;CAI Nai-qiong¹;ZHU Zhang-ming¹;YANG Yin-tang¹

(1. Research Inst. of Microelectronics, Xidian Univ., Xi'an 710071， China;
2. Aicestar Technology Suzhou Company, Suzhou 215021， China)

Received:2009-12-15 Online:2010-10-20 Published:2010-10-11
Contact: TONG Xing-yuan E-mail:mayxt@126.com

Abstract

Abstract:

This paper focuses on the research on the SAR (Successive-Approximation-Register) A／D converter. An R-C-R combination based SAR A／D conversion approach is discussed and a 12-bit 1MSamples/s SAR A／D converter is realized with this approach in the UMC 90nm CMOS process. In circuit design, the matching requirement for the capacitor array is alleviated by utilizing a reusable two-segment resistor string. In layout design, a special resistor layout design method is used to reduce impact on linearity from the mismatch of connection resistors. Metal finger capacitors are adopted to improve technology compatibility and reduce the cost. With a 3.3V analog supply and a 1.0V digital supply, the differential non-linearity of this converter is measured to be 0.78LSB (Least-Significant-Bit). At the sampling rate of 1MSamples/s and the input frequency of 10kHz, the ENOB (Effective-Number-of-Bits) is measured to be 10.3 and the power dissipation is measured to be less than 10mW including that of the output drivers. The active area of the converter is about 0.31mm². This converter can satisfy the embedded SoC (System-on-Chip) applications.

Key words: A／D converter, successive approximation register, two-segment resistor string, metal finger capacitor, low cost

TONG Xing-yuan;CHEN Shan;CAI Nai-qiong;ZHU Zhang-ming;YANG Yin-tang. 12-bit SAR A／D converter with an R-C-R hybrid architecture[J].J4, 2010, 37(5): 904-910.

References

[1] Ginsburg B P, Chandrakasan A P. Highly Interleaved 5-bit, 250-MSample／s, 1.2-mW ADC with Redundant Channels in 65-nm CMOS [J] . IEEE Journal of Solid-State Circuits, 2008, 43(10): 2641-2650.
[2] Analog Devices, AD7877-Touch Screen Controller [R／OL] . [2009-12-10] . http://www.analog.com／en／analog-to-digital-converters／ad-converters／ad7877／products／product.html.
[3] Tong X Y, Yang Y T, Zhu Z M, et al. A 10-bit Low Power SAR A／D Converter Based on 90nm CMOS [J] . Chinese Journal of Semiconductors, 2009, 30(10): 105008-8.
[4] Larivee B J, Chie W Y, Gebara F H. A 10MS／s 10-Bit Successive Approximation Register Analog to Digital Converter [D] . Michigan: University of Michigan, 2002.
[5] Promitzer G. 12-bit Low-Power Fully Differential Switched Capacitor Non-calibrating Successive Approximation ADC with 1 MS／s [J] . IEEE Journal of Solid-State Circuits, 2001, 36(7): 1138-1143.
[6] Zhong L G, Yang H G, Zhang C. Design of an Embedded CMOS CR SAR ADC for Low Power Applications in Bio-Sensor SOC [C] //ASICON 2007. Guilin: IEEE, 2007: 668-671.
[7] Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1V 3.8μW 100kS／s SAR ADC with Time-Domain Comparator [C] //ISSCC Dig Tech Papers. San Francisco: IEEE, 2008: 246-247.
[8] Cao Z, Yan S, Li Y. An 32mW 1.25GS／s 6b 2b／step SAR ADC in 0.13μm CMOS [C] //ISSCC Dig Tech Papers. San Francisco: IEEE, 2008: 542-543.
[9] Razavi B. Design of Analog CMOS Integrated Circuits[M] . Asia: McGraw-Hill, 2005: 423.
[10] Fotouhi B, Hodges D A. High-Resolution A／D Conversion in MOS／LSI [J] . IEEE Journal of Solid-State Circuits, 1979, 14(6): 920-926.
[11] Mognon V R, Carlos A R. Capacitive-SAR ADC Input Offset Reduction by Stray Capacitance Compensation [C] //Proceedings of the 7th International Caribbean Conference on Devices, Circuits and Systems. Mexico: IEEE, 2008: 1-6.
[12] Doernberg J, Lee H S, Hodges D A. Full Speed Testing of A／D Converters [J] . IEEE Journal of Solid State Circuits, 1984, 19(6): 820-827.

12-bit SAR A／D converter with an R-C-R hybrid architecture

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