考虑工艺波动的两相邻耦合RC互连串扰噪声估计

doi:10.3969/j.issn.1001-2400.2010.06.018

J4 ›› 2010, Vol. 37 ›› Issue (6): 1082-1087+1131.doi: 10.3969/j.issn.1001-2400.2010.06.018

• Original Articles • Previous Articles Next Articles

Crosstalk noise estimation of two adjacent RC interconnects with process variations

DONG Gang;YANG Yang;CHAI Chang-chun;YANG Yin-tang

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2010-04-22 Online:2010-12-20 Published:2011-01-22
Contact: DONG Gang E-mail:gdong@mail.xidian.edu.cn

Abstract

Abstract:

Based on the six-node template circuit of coupling interconnects, a novel method for analyzing the statistical crosstalk noise of RC interconnects with process variations is proposed. Analytical expressions for mean and standard deviation of the statistical crosstalk noise are derived for a given fluctuation range of interconnect parameters. Simulation results show that the time of calculation is greatly shortened with a good calculating precision using the proposed statistical model as compared to the widely used Monte Carlo method. Calculated results also indicate that the errors of the mean and standard deviation are less than 2.36％ and 7.23％ respectively.

Key words: process variations, RC interconnect, crosstalk noise, statistical model

DONG Gang;YANG Yang;CHAI Chang-chun;YANG Yin-tang. Crosstalk noise estimation of two adjacent RC interconnects with process variations[J].J4, 2010, 37(6): 1082-1087+1131.

References

[1] 李建伟, 董刚, 杨银堂, 等. 工艺波动致RLC互连延时极值分析[J]. 西安电子科技大学学报, 2009, 36(2):301-307.
Li Jianwei, Dong Gang, Yang Yintang, et al. Extreme Value Analysis of RLC Interconnect Delay Induced by Process Variations[J]. Journal of Xidian University, 2009, 36(2): 301-307.
[2] Raghunandan C, Sainarayanan K S, Srinivas M B. Impact of Process Variations on Bus-Encoding Schemes for Delay Minimization in VLSI Interconnects[C]//IEEE Workshop on Signal Propagation on Interconnects (SPI). Genova: IEEE, 2007: 254-258.
[3] Huebbers F, Dasdan A, Ismail Y. Computation of Accurate Interconnect Process Parameter Values for Performance Corners under Process Variations[C]//Design Automation Conference. San Francisco: IEEE, 2006: 797-800.
[4] Qu H, Kong L, Xu Y S, et al. Finite-Element Computation of Sensitivities of Interconnect Parasitic Capacitances to the Process Variation in VLSI[J]. IEEE Trans on Magnetics, 2008, 44(6): 1386-1389.
[5] 尚玉玲,李玉山. 高速互连渐进式串扰故障激励测试模型研究[J]. 西安电子科技大学学报, 2009, 36(2):314-321.
Shang Yuling, Li Yushan. Study of the Incremented Crosstalk Stimulation Testing Model of High-Speed Interconnect[J]. Journal of Xidian University, 2009, 36(2): 314-321.
[6] Vittal A, Marek-Sadowska M. Crosstalk Reduction for VLSI[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 1997, 16(3): 290-297.
[7] Vittal A, Chen L H, Marek-Sadowska M, et al. Crosstalk in VLSI Interconnects[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 1999, 18(12): 1817-1824.
[8] Cong J, Pan D Z, Srinivas P V. Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization[C]//Asia and South Pacific Design Automation Conference. Yokohama: IEEE, 2001:373-378.
[9] Ding L, Blaauw D, Mazumder P. Accurate Crosstalk Noise Modeling for Early Signal Integrity[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(5): 627-634.
[10] Wang Z, Dong G, Yang Y T, et al. Crosstalk Noise Voltage of Coupling RC Interconnects with Temperature Distribution[J]. Chinese Journal of Electronics, 2010, 19(1):43-47.
[11] Delorme N, Belleville M, Chilo J. Inductance and Capacitance Analytic Formulas for VLSI Interconnects[J]. Electronics Letters, 1996, 32(11): 996-997.
[12] Agarwal K, Agarwal M, Sylvester D, et al. Statistical Interconnect Metrics for Physical Design Optimization[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(7): 1273-1288．
[13] ITRS. Interconnect[R/OL].[2007-12-15]. http://www.itrs.net.

Crosstalk noise estimation of two adjacent RC interconnects with process variations

PDF (PC)

Like

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 5

Metrics

Comments

Recommended 0

[1]	LIU Pei;SHUI Penglang;GUO Yongming;LI Ning. Analysis of the statistical model with the two-dimensional cumulant feature applying to modulation classification [J]. J4, 2014, 41(2): 44-50.
[2]	TANG Hualian;ZHUANG Yiqi;ZHANG Li;JING Xin;DU Yongqian. Design of a trimmed current reference with a low temperature drift [J]. J4, 2013, 40(4): 130-136.
[3]	SHENG Jialian;ZHANG Lei;XING Mengdao;BAO Zheng. Super-resolution ISAR imaging method with sparse statistics [J]. J4, 2012, 39(6): 55-60.
[4]	YANG Yang;CHAI Chang-chun;DONG Gang;YANG Yin-tang;LENG Peng. Modeling and calculating of interconnect delay by considering the influence of inductance effect and process fluctuations [J]. J4, 2010, 37(3): 513-519.
[5]	LI Jian-wei;DONG Gang;YANG Yin-tang;WANG Zeng. Extreme value analysis of RLC interconnect delay induced by process variations [J]. J4, 2009, 36(2): 301-307.