90nm CMOS工艺下电压触发的ESD检测电路

doi:10.3969/j.issn.1001-2400.2015.03.010

Abstract

Abstract:

Two voltage triggered electrostatic discharge (ESD) detection circuits are proposed in a 90nm 1V CMOS process, which can avoid the gate leakage current issue in the nanometer CMOS process. The proposed circuits include feedback loops to enhance the ESD trigger efficiency, and also add turn-off mechanisms, which can turn off the feedback when they are turned on for some unknown reasons and cannot be latched on. Under 3V ESD simulation, the circuits can inject 28mA trigger currents into the clamp device. Under the 25℃ normal operating condition the leakage current is 42nA and 45nA , respectively. Simulation result shows that the circuits can be successfully used in nanometer CMOS process ESD protection.

Key words: feedback, detection circuit, electrostatic discharge (ESD), voltage triggered

YANG Zhaonian;LIU Hongxia;ZHU Jia;FEI Chenxi. Voltage triggered ESD detection circuits in a 90nm CMOS process[J].J4, 2015, 42(3): 54-60.

References

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Voltage triggered ESD detection circuits in a 90nm CMOS process

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