[1] ZHAO Z Y, LI X Y, CHANG W G. LFM-CW Signal Generator Based on Hybrid DDS-PLL Structure[J]. Electronics Letters, 2013, 49(6): 381-382.
[2] ZHOU Z H, LA RUE G S. A 12-bit Nonlinear DAC for Direct Digital Frequency Synthesis[J]. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2008, 55(9): 2459-2468.
[3] AVITABILE G, CANNONE F, VANIA A. Phase Shifter Based on DDS-driven Offset-PLL[J]. Electronics Letters, 2006, 42(25): 1438-1439.
[4] GHOSH M, CHIMAKURTHY L S J, DAI F F, et al. A Novel DDS Architecture Using Nonlinear ROM Addressing with Improved Compression Ratio and Quantization Noise[C]//Proceedings of the 2004 IEEE International Symposium on Circuits and Systems. Piscataway: IEEE, 2004: II705-II708.
[5] 刘马良, 朱樟明, 郭旭龙, 等. 一种4路内插CORDIC的14位吉赫兹DDS IP核[J]. 西安电子科技大学学报,2013, 40(6): 62-66.
LIU Maliang, ZHU Zhangming, GUO Xulong, et al. 4 Channel Interpolated 14bit High Speed CORDIC DDS IP Core[J]. Journal of Xidian University, 2013, 40(6): 62-66.
[6] 张俊安, 李广军, 张瑞涛, 等. 单片直接数字频率合成器产品发展综述[J]. 微电子学, 2015, 45(5): 676-680.
ZHANG Jun'an, LI Guangjun, ZHANG Ruitao, et al. An Overview of Direct Digital Frequency Synthesizer IC[J]. Microelectronics, 2015, 45(5): 676-680.
[7] de CARO D, STROLLO A G M. High Performance Direct Digital Frequency Synthesizers Using Piecewise Polynomial Approximation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2005, 52(2): 324-337.
[8] 屈八一, 宋焕生, 周渭, 等. 一种新型不同频直接鉴相的锁相环[J]. 西安电子科技大学报, 2014, 41(2): 172-177.
QU Bayi, SONG Huansheng, ZHOU Wei, et al. Novel Phase Locked Loop with Direct Phase Detection for Two Frequency Different Signals[J]. Journal of Xidian University, 2014, 41(2): 172-177.
[9] LANGLOIS J M P, AL-KHALILI D. Phase to Sinusoid Amplitude Conversion Techniques for Direct Digital Frequency Synthesis[J]. IEE Proceedings: Circuits, Devices and Systems, 2004, 151(6): 519-528.
[10] GALLEANI L, TAVELLA P. Robust Detection of Fast and Slow Frequency Jumps of Atomic Clocks[J]. IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, 2017, 64(2): 475-485.
[11] ZHAN L, LIU Y, YAO W, et al. Utilization of Chip-scale Atomic Clock for Synchrophasor Measurements[J]. IEEE Transactions on Power Delivery, 2016, 31(5): 2299-2300.
[12] 白丽娜, 周渭, 都倩倩, 等. 一种新颖的铯原子钟频率信号处理的线路技术[J]. 西安电子科技大学学报, 2015, 42(2): 71-76.
BAI Lina, ZHOU Wei, DU Qianqian, et al. Novel Cesium Atomic Clock Frequency Signal Processing Circuit Technology[J]. Journal of Xidian University, 2015, 42(2): 71-76. |