Abstract:

It is difficult to increase the output bandwidth and memory depth of an arbitrary waveform generator. A scheme for the data path of the high speed arbitrary waveform generator based on the Field Programmable Gate Array (FPGA) has been developed. In this scheme, the multi-chip synchronous dynamic random access memory synchronous output and parallel-to-serial conversion technology are used to improve the output bandwidth and memory depth of the data path. The data path implements data writing, reading, parallel-to-serial conversion, framing, 8bit/10bit encoding, and serialization based on the Vivado platform. The processed waveform data is serially outputted through FPGA's transceiver according to the JESD204B transmission protocol. Simulation results show that the output waveform data is exactly the same as the processed waveform data, which verifies the correctness of the data path. Experimental results show that the data path achieves a 12 GHz sampling rate, a 16 bit vertical resolution, and a 4 Gsa waveform memory. The data path of the arbitrary waveform generator is effective and reliable.

Key words: waveform generation, field programmable gate array, parallel-to-serial conversion, serial transmission