Journal of Xidian University ›› 2019, Vol. 46 ›› Issue (5): 48-54.doi: 10.19665/j.issn1001-2400.2019.05.007

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Optimization of the voltage noise induced by the power gating technique

WANG Leilei1,2,3,WANG Lu1   

  1. 1. School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China
    2. Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
    3. School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
  • Received:2019-04-20 Online:2019-10-20 Published:2019-10-30

Abstract:

Since voltage noise could threaten the correct execution of the chip function, in this paper a system-level power gating sequence is proposed to reduce the induced voltage noise by turning on circuit modules with power gating. By establishing and solving the mixed integer linear programming problem, we can obtain the optimal order and time interval of multi-circuit modules to connect the power grid within the specified time constrain, so that the introduced voltage noise can be minimized. Experimental results show that our power gating schedules can reduce the introduced voltage noise by over 30%, and we also get the trade-off between the time constrain and the introduced voltage noise. Hence, our power gating sequence could significantly reduce the induced power noise under different time constrains.

Key words: power grid, voltage noise, power gating, turn-on sequence, mixed integer linear programming

CLC Number: 

  • TN47