Journal of Xidian University ›› 2020, Vol. 47 ›› Issue (4): 24-30.doi: 10.19665/j.issn1001-2400.2020.04.004
Previous Articles Next Articles
QU Bayi1(),LIU Yehao1,ZHANG Taojing1,LIU Wei1,YU Dongsong1,ZHOU Wei2
Received:
2020-03-03
Online:
2020-08-20
Published:
2020-08-14
CLC Number:
QU Bayi,LIU Yehao,ZHANG Taojing,LIU Wei,YU Dongsong,ZHOU Wei. Scheme for miniature time difference measurement with a high resolution and a large range[J].Journal of Xidian University, 2020, 47(4): 24-30.
"
0℃的10次测量结果及其 均值和方差 | 10℃的10次测量结果及其 均值和方差 | 20℃的10次测量结果及其 均值和方差 | 30℃的10次测量结果及其 均值和方差 |
---|---|---|---|
1000000000601 | 1000000000628 | 1000000000609 | 1000000000637 |
1000000000603 | 1000000000629 | 1000000000625 | 1000000000624 |
1000000000614 | 1000000000614 | 1000000000633 | 1000000000610 |
1000000000610 | 1000000000605 | 1000000000643 | 1000000000605 |
1000000000603 | 1000000000601 | 1000000000602 | 1000000000640 |
1000000000606 | 1000000000639 | 1000000000641 | 1000000000601 |
1000000000629 | 1000000000617 | 1000000000621 | 1000000000605 |
1000000000615 | 1000000000602 | 1000000000618 | 1000000000602 |
1000000000645 | 1000000000609 | 1000000000629 | 1000000000631 |
1000000000633 | 1000000000601 | 1000000000610 | 1000000000625 |
(1000000000616,14) | (1000000000615,13) | (1000000000623,13) | (1000000000618,14) |
[1] | ENOMOTO R, IIZUKA T, KOGA T, et al. A 16-bit 2.0-ps Resolution Two-step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage with Built-in Coarse Gain Calibration[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2019,27(1):11-19. |
[2] |
LEVSKI D, WÄNY M, CHOUBEY B, et al. A 1-μs Ramp Time 12-bit Column-parallel Flash TDC-interpolated Single-slope ADC with Digital Delay Element Calibration[J]. IEEE Transactions on Circuits and Systems-I: Regular Papers, 2019,66(1):54-67.
doi: 10.1109/TCSI.2018.2846592 |
[3] | 屈八一, 程腾, 俞东松, 等. 一种高性能的全数字锁相环设计方案[J]. 西安电子科技大学学报, 2019,46(1):112-116. |
QU Bayi, CHENG Teng, YU Dongsong, et al. Design Scheme for an All-digital Phase Locked Loop with a High Performance[J]. Journal of Xidian University, 2019,46(1):112-116. | |
[4] | 偶晓娟, 周渭, 易韦韦, 等. 精密频率测量边沿效应的特性分析[J]. 西安电子科技大学学报, 2016,43(3):144-148. |
OU Xiaojuan, ZHOU Wei, YI Weiwei, et al. Characteristic Analysis of the Border Effect in Precision Frequency Measurement[J]. Journal of Xidian University, 2016,43(3):144-148. | |
[5] |
SEONG T H, LEE Y S, YOO S E, et al. A 320-fs RMS Jitter and -75-dBc Reference-Spur Ring-DCO-based Digital PLL Using an Optimal-threshold TDC[J]. IEEE Journal of Solid-State Circuits, 2019,54(9):2501-2512.
doi: 10.1109/JSSC.4 |
[6] |
KERANEN P, KOSTAMOVAARA J. 256×TDC Array with Cyclic Interpolators Based on Calibration-free 2×Time Amplifier[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,66(2):524-533.
doi: 10.1109/TCSI.8919 |
[7] |
LEE M E, KIM S W, PARK H J, et al. A 0.0043-mm 2 0.3-1.2V Frequency-scalable Synthesized Fractional-N Digital PLL with a Speculative Dual-referenced Interpolating TDC[J]. IEEE Journal of Solid-State Circuits, 2019,54(1):99-108.
doi: 10.1109/JSSC.2018.2876464 |
[8] |
WU J, ZHANG P B, SHI S F, et al. A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,66(11):1805-1809.
doi: 10.1109/TCSII.8920 |
[9] |
DAVIDE T, DAVIDE P, FEDERICA V, et al. Eight-channel 21 ps Precision 10 μs Range Time-to-digital Converter Module[J]. IEEE Transactions on Instrumentation and Measurement, 2016,65(2):423-430.
doi: 10.1109/TIM.2015.2485378 |
[10] |
HUANG Z Q, LUONG H C. An 82-107.6-GHz Integer-N ADPLL Employing a DCO with Split Transformer and Dual-path Switched-capacitor Ladder and a Clock-Skew-sampling Delta-sigma TDC[J]. IEEE Journal of Solid-State Circuits, 2019,54(2):358-367.
doi: 10.1109/JSSC.2018.2876462 |
[11] | 屈八一, 张蕊, 张鑫, 等. 新型的精密时差测量技术[J]. 西安电子科技大学学报, 2015,42(6):152-157. |
QU Bayi, ZHANG Rui, ZHANG Xin, et al. Novel Short Time Interval Measurement Technology with High Precision[J]. Journal of Xidian University, 2015,42(6):152-157. | |
[12] | 卜朝晖, 常仙云, 陈文星, 等. 基于可触发环形振荡器的高精度时间间隔测量[J]. 仪器仪表学报, 2019,40(5):10-18. |
BU Zhaohui, CHANG Xianyun, CHEN Wenxing, et al. High-precision Time Interval Measurement Based on Trigger Able Ring Oscillator[J]. Chinese Journal of Scientific Instrument, 2019,40(5):10-18. | |
[13] |
CHENG Z, ZHENG X Q, DEEN M J, et al. Recent Developments and Design Challenges of High-performance Ring Oscillator CMOS Time-to-digital Converters[J]. IEEE Transactions on Electron Devices, 2016,63(1):235-251.
doi: 10.1109/TED.2015.2503718 |
[14] | 刘正阳, 刘音华, 李孝辉. 基于FPGA的TDC系统偏差修正方法的研究[J]. 时间频率学报, 2019,42(2):142-150. |
LIU Zhengyang, LIU Yinhua, LI Xiaohui. TDC System Deviation Correction Method Research Based on FPGA[J]. Journal of Time and Frequency, 2019,42(2):142-150. | |
[15] |
WU J X, DENG W, CHEN Z P, et al. A 77-GHz Mixed-mode FMCW Generator Based on a Vernier TDC with Dual Rising-edge Fractional-phase Detector[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,67(1):60-73.
doi: 10.1109/TCSI.8919 |
[16] |
WON J Y, KWON S II, YOON H S, et al. Dual-phase Tapped-delay-line Time-to-digital Converter with On-the-fly Calibration Implemented in 40 nm FPGA[J]. IEEE Transactions on Biomedical Circuits and Systems, 2016,10(1):231-242.
doi: 10.1109/TBCAS.2015.2389227 pmid: 25775497 |
[17] | 许龙飞, 罗丹, 周渭, 等. 一种全面响应时间的频率稳定度测量[J]. 西安电子科技大学学报, 2018,45(1):72-75. |
XU Longfei, LUO Dan, ZHOU Wei, et al. Method of a Comprehensive Response Time of Frequency Stability[J]. Journal of Xidian University, 2018,45(1):72-75. | |
[18] |
ZHANG M L, CHAN C H, ZHU Y, et al. A 0.6-V 13-bit 20-MS/s Two-step TDC-assisted SAR ADC with PVT Tracking and Speed-enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019,54(12):3396-3409.
doi: 10.1109/JSSC.4 |
[19] |
LIU M L, LIU H Z, LI X Z, et al. A 60-m Range 6.16-mW Laser-power Linear-mode LiDAR System with Multiplex ADC/TDC in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,67(3):753-764.
doi: 10.1109/TCSI.8919 |
[1] | HE Shiyang,LI Hui,LI Fenghua. Optimization and implementation of the SM4 on FPGA [J]. Journal of Xidian University, 2021, 48(3): 155-162. |
[2] | NGUYEN Van-Truong,CAI Jueping,WEI Linyu,CHU Jie. Low complexity probability-based piecewise linear approximation of the sigmoid function [J]. Journal of Xidian University, 2020, 47(3): 58-65. |
[3] | WANG Dekui. Approach to FPGA placement using resource negotiation [J]. Journal of Xidian University, 2019, 46(6): 17-22. |
[4] | XUE Dekuan,LI Guoyang,PAN Xue,FAN Wei,LI Xuechun,ZHU Jianqiang. Design of the data path of the high speed arbitrary waveform generator [J]. Journal of Xidian University, 2019, 46(3): 173-179. |
[5] | ZHENG Ling;QIU Zhiliang;SUN Shiyong;PAN Weitao;WANG Weina;ZHANG Zhiyi. Two-step multiple flow table construction algorithm in the software-defined network [J]. Journal of Xidian University, 2018, 45(5): 25-31. |
[6] | ZHAO Boran;ZHANG Li;SHI Guangming;HUANG Rong;XU Xinran. Design of the programmable neural network processor based on the transport triggered architecture [J]. Journal of Xidian University, 2018, 45(4): 92-98. |
[7] | GUO Qiang;LIU Bo;SI Shengping;LIU Hui;JIANG Yingfu;ZHANG Heng. SRAM-FPGA SEU mitigation method and prediction [J]. Journal of Xidian University, 2018, 45(1): 112-116. |
[8] | CHEN Zhenhai;YU Zongguang;LI Xiankun;WEI Jinghe;HUANG Songren;SU Xiaobo. High precision voltage reference generator for 16-bit 100MS/s ADC [J]. Journal of Xidian University, 2017, 44(3): 127-132+180. |
[9] | DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation [J]. Journal of Xidian University, 2016, 43(2): 35-40. |
[10] | BAI Lina;ZHOU Wei;DU Qianqian;CHEN Jiao;CHEN Hongjie . Novel cesium atomic clock frequency signal processing circuit technology [J]. J4, 2015, 42(2): 71-76. |
[11] | LAI Xin-quan;HAO Qi;YUAN Bing;CHEN Lei;YE Qiang. High precision bandgap reference with 2nd order curvature compensation [J]. J4, 2010, 37(5): 911-915+933. |
[12] |
WANG Hai;ZHOU Wei;LIU Chang-sheng;WANG Shui-sheng.
Novel short time interval measurement method [J]. J4, 2008, 35(2): 267-271. |
[13] |
JIN Wei-sheng;ZENG Xiao-dong;AN Yu-ying.
A method to improve the time resolution of the pulse laser range finder using an A/D converter and a look-up table [J]. J4, 2004, 31(5): 666-669. |
|