[1] |
谷大武, 张驰, 陆相君. 密码系统的侧信道分析:进展与问题[J]. 西安电子科技大学学报, 2021, 48(1):14-21.
|
|
GU Dawu, ZHANG Chi, LU Xiangjun. Progress of and Some Comments on The Research of Side-Channle Attack for Cryptosystems[J]. Journal of Xidian University, 2021, 48(1):14-21.
|
[2] |
张璐, 慕德俊, 胡伟, 等. 能量隐通道安全高层综合设计方法[J]. 西安电子科技大学学报, 2020, 47(4):64-69.
|
|
ZHANG Lu, MU Dejun, HU Wei, et al. High-Level Synthesis Design Flow for Power Side-Channel Security[J]. Journal of Xidian University, 2021, 47(4):64-69.
|
[3] |
QUISQUATER J J, SAMYDE D. Electromagnetic Analysis (ema):Measures and Counter-Measures for Smart Cards[C]// International Conference on Research in Smart Cards.Heidelberg:Springer, 2001:200-210.
|
[4] |
SINGH A, KAR M, CHEKURI V C K, et al. Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO[J]. IEEE Journal of Solid-State Circuits, 2020, 55(2):478-493.
doi: 10.1109/JSSC.2019.2945944
|
[5] |
PAMMU A A, CHONG K S, GWEE B H. Highly Secured State-Shift Local Clock Circuitto Countermeasure Against Side Channel Attack[C]// 2017 IEEE International Symposium on Circuits and Systems.Piscataway:IEEE, 2017:2226-2229.
|
[6] |
PAMMU A A, CHONG K S, GWEE B H. Highly Secured Arithmetic Hiding Based S-Boxon AES-128 Implementation[C]// 2016 International Symposium on Integrated Circuits.Piscataway:IEEE, 2016:1-4.
|
[7] |
HE J, MA H, GUO X, et al. Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations[C]// 2020 25th Asia and South Pacific Design Automation Conference.Piscataway:IEEE, 2020:62-67.
|
[8] |
MA H, HE J, LIU Y, et al. Security-Driven Placement and Routing Tools for Electromagnetic Side Channel Protection[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 40(6):1077-1089.
doi: 10.1109/TCAD.2020.3024938
|
[9] |
CHARI S, JUTLA C S, RAO J R, et al. Towards Sound Approaches to Counteract Power-Analysis Attacks[C]// Annual International Cryptology Conference.Heidelberg:Springer, 1999:398-412.
|
[10] |
CORON J S, GREUET A, ZEITOUN R. Side-Channel Masking with Pseudo-Random Generator[C]// Annual International Conference on the Theory and Applications of Cryptographic Techniques.Heidelberg:Springer, 2020:342-375.
|
[11] |
TIRI K, VERBAUWHEDE I. A Logic Level Design Methodologyfor a Secure DPA Resistant ASIC or FPGA Implementation[C]// Proceedings Design,Automation and Test in Europe Conference and Exhibition.Piscataway:IEEE, 2004:246-251.
|
[12] |
LEVI I, BELLIZIA D, BOL D, et al. Ask Less,Get More:Side-Channel Signal Hiding,Revisited[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2020, 67(12):4904-4917.
doi: 10.1109/TCSI.2020.3005338
|
[13] |
KOUSHANFAR F. Provably Secure Active IC Metering Techniquesfor Piracy Avoidance and Digital Rights Management[J]. IEEE Transactions on Information Forensics and Security, 2011, 7(1):51-63.
doi: 10.1109/TIFS.2011.2163307
|
[14] |
ZHANG J, LIN Y, LYU Y, et al. A PUF-FSM Binding Schemefor FPGA IP Protection and Pay-Per-Device Licensing[J]. IEEE Transactions on Information Forensics and Security, 2015, 10(6):1137-1150.
doi: 10.1109/TIFS.2015.2400413
|
[15] |
BUCCI M, GUGLIELMO M, LUZZI R, et al. A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors[C]// International Workshop on Power and Timing Modeling,Optimization and Simulation.Heidelberg:Springer, 2004:481-490.
|
[16] |
LI G, IYER V, ORSHANSKY M. Securing AES Against Localized EM Attacks Through Spatial Randomization of Dataflow[C]// 2019 IEEE International Symposium on Hardware Oriented Security and Trust.Piscataway:IEEE, 2019:191-197.
|
[17] |
HETTWER B, DAS K, LEGER S, et al. Lightweight Side-Channel Protection Using Dynamic Clock Randomization[C]// 2020 30th International Conference on Field-Programmable Logic and Applications.Piscataway:IEEE, 2020:200-207.
|
[18] |
MANGARD S. Hardware Countermeasures Against DPA-A Statistical Analysis of Their Effectiveness[C]// Cryptographers’Track at the RSA Conference.Heidelberg:Springer, 2004:222-235.
|
[19] |
VALTCHANOV B, AUBERT A, BERNARD F, et al. Modeling and Observing the Jitter in Ring Oscillators Implemented in FPGAs[C]// 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.Piscataway:IEEE, 2008:1-8.
|