一种面向片上网络的多时钟路由器设计

doi:10.3969/j.issn.1001-2400.2011.02.026

Abstract

Abstract:

The router is a core element of the NoCs(Network-on-Chips). Aiming at NoC communication issues among different clock domains, the paper proposes a multi-clock router microarchitecture, which applies to 2D mesh topology NoC and uses dual-clock asynchronous FIFOs(First In First Out) instead of cross-clock domain interface circuits in usual routers. Designed by the Verilog HDL, the router's integrated results on FPGA show that it uses fewer resources and operates at a high frequency of up to 475.29MHz, effectively increasing the data transmission rate. Based on SMIC 0.13μm CMOS technology, by comparing the integrated results of routers with different FIFO depth values, impacts of the buffer size on the router's performance and cost are analyzed further.

Key words: network-on-chip, router, multi-clock

CLC Number:

LIU Yi;YANG Yintang;ZHOU Donghong. Multi-clock router designed for the network-on-chip[J].J4, 2011, 38(2): 146-150.

References

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Multi-clock router designed for the network-on-chip

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