[1] Benini L, De Micheli G. Networks on Chips: a New SoC Paradigm[J]. Computer, 2002, 35(1): 70-78.
[2] 刘毅, 杨银堂, 周东红. 一种面向片上网络的多时钟路由器设计[J]. 西安电子科技大学学报, 2011, 38(2): 146-150.
Liu Yi, Yang Yintang, Zhou Donghong. Multi-clock Router Designed for the Network-on-chip[J]. Journal of Xidian University, 2011, 38(2): 146-150.
[3] Ogras U Y, Hu J, Marculescu R. Key Research Problems in NoC Design: a Holistic Perspective[C]//the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Jersey City: IEEE, 2005: 69-74.
[4] Hu J, Marculescu R. Energy-and Performance-aware Mapping for Regular NoC Architectures[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(4): 551-562.
[5] Dong Yiping, Wang Yang, Lin Zhen, et al. High Performance and lOw Latency Mapping for Neural Network into Network on Chip Architecture[C]//IEEE 8th International Conference on ASIC(ASICON). Changsha: IEEE, 2009: 891-894.
[6] Marcon C, Borin A, Susin A, et al. Time and Energy Efficient Mapping of Embedded Applications onto NoCs[C]//Asia and South Pacific Design Automation Conference(ASP-DAC). Shanghai: ACM, 2005: 33-38.
[7] Morgan A A, Elmiligi H, El-Kharashi M W, et al. Multi-objective Optimization for Networks-on-Chip Architectures Using Genetic Algorithms[C]//IEEE International Symposium on Circuits and Systems (ISCAS). Paris: IEEE, 2010: 3725-3728.
[8] Karaboga D, Basturk B. On the Performance of Artificial Bee Colony (ABC) Algorithm[J]. Applied Soft Computing, 2008, 8(1): 687-697.
[9] Hu J, Marculescu R. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures[C]//Design, Automation and Test in Europe Conference and Exhibition. Munich: IEEE, 2003: 688-693.
[10] 周干民, 尹勇生, 胡永华, 等. 基于蚁群优化算法的NoC映射[J]. 计算机工程与应用, 2005, 41(18): 7-10.
Zhou Ganmin, Yin Yongsheng, Hu Yonghua, et al. NoC Mapping Based on Ant Colony Optimization Algorithm[J]. Computer Engineering and Applications, 2005, 41(18): 7-10.
[11] Van Der Tol E B, Jaspers E G T. Mapping of MPEG-4 Decoding on a Flexible Architecture Platform[C]//SPIE-Media Processors: 4674. San Jose: SPIE, 2002: 1-13.
[12] Dumitriu V, Khan G N. Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs[J]. IEEE Trans on Very Large Scale Integration (VLSI) Systems, 2009, 17(10): 1433-1446.
[13] Gaur M S, Al-Hashimi B M, Laxmi V, et al. NIRGAM: a Simulator for NoC Interconnect Routing and Applications' Modeling[R/OL]. [2011-05-20]. http://www.nirgam.ecs.soton.ac.uk.
[14] Chen Xuning, Peh L S. Leakage Power Modeling and Optimization in Interconnection Networks[C]//the International Symposium on Low Power Electronics and Design(ISLPED). Seoul: ACM, 2003: 90-95. |