Journal of Xidian University

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ESD power-rail clamp circuit with a 5V power in the 3.3V CMOS process

CHEN Diping;DONG Gang   

  1. (College of Physics and Microelectronics Science, Hunan Univ., Changsha 410082, China)
  • Received:2017-09-28 Online:2018-10-20 Published:2018-09-25

Abstract:

Considering the 5V power supply, a novel ESD(electrostatic discharge) circuit with a 5V power rail based on a conventional GG-NMOS (Gate-Ground NMOS) ESD power-rail clamp circuit is designed by the method of level shifters and the low follow current in the 3.3V CMOS process to avoid a higher cost under the high-voltage process. Due to progressively driving and releasing steps of the optimized circuit, the leakage current is decreased in a regular operation. Moreover, the circuit is verified with simulations based on models in the SMIC's 0.18μm CMOS process technology library and the fabricated ESD power-rail clamp circuit has passed the HBM (Human Body Model) ESD test at ±4000V. The circuits can be successfully used for the 5V power rail ESD protection.

Key words: electro-static discharge, protection circuits, hierarchical driver, leakage current