Based on the lumped interconnection power model, a distributed dynamic power model is presented first. Then by adopting a non-uniform interconnection structure, a novel optimal interconnection power model is proposed, which is constrained by delay, bandwidth, area, minimum interconnection width and minimum interconnection space. The validity of the proposed model is verified by 90nm and 65nm CMOS technology. The results indicate that the proposed model can reduce power consumption as high as 30%, with the delay, area, bandwidth not deteriorated. The proposed optimal model can be used for the interconnection optimal design in large scale integrated circuits.