[1] Europe, Japan, Korea, Taiwan, USA. Semiconductor Industry Association 2012 International Technology Roadmap for Semiconductors 2012[DB/OL]. [2013-01-02]. http://www.itrs.net.zdz.
[2] Uchino T, Cong J. An Interconnect Energy Model Considering Coupling Effects[J]. IEEE Transactions Computer-Aided Design of Integration Circuits System, 2002, 21(7): 763-776.
[3] 朱樟明, 钟波, 杨银堂. 基于RLC π 型等效模型的互连网络精确焦耳热功耗计算[J]. 物理学报, 2010, 59(7): 4895-4900.
Zhu Zhangming, Zhong Bo, Yang Yintang. An Accurate Joule Heat Model of RLC Interconnect Based on π Equivalent Circuit[J]. Acta Physica Sinica, 2010, 59(7): 4895-4900.
[4] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Method for On-Chip VLSI Interconnects[C]//Proceedings of the 2nd International Conference on Emerging Applications of Information Technology. Piscataway: IEEE, 2011: 379-382.
[5] Zhou Q, Mohanram K. Elmore Model for Energy Estimation in RC Trees[C]//43rd ACM/IEEE Design Automation Conference. Piscataway: IEEE, 2006: 965-970.
[6] Kar R, Maheshwari V, Mondal S, et al. A Novel Power Estimation Method for On-Chip VLSI Distributed RLCG Global Interconnects Using Model Order Reduction Technique[C]//International Conference on Advances in Computer Engineering. Piscataway: IEEE, 2010: 105-109.
[7] Chen C P, Chen Y P, Wong D F. Optimal Wire-Sizing Formula Under the Elmare Delay Model[C]//Proceedings of 33rd Design Automation Conference. Piscataway: IEEE, 1996: 487-490.
[8] Lee Y M, Chen C C P, Wong D F. Optimal Wire-Sizing Function Under the Elmore Delay Model with Bounded Wire Sizes[J]. IEEE Transactions Circuits System-Ⅰ: Fundamental Theory and Application, 2002, 49(11): 1671-1677.
[9] EI Moursy M A, Friedman E G. Exponentially Tapered H-Tree Clock Distribution Networks [J]. IEEE Transactions Very Large Scale Integration System, 2005, 13(8): 971-975.
[10] Ni M, Memik S O. Self-Heating Aware Optimal Wire Sizing Under Elmore Delay Model[C]//Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Piscataway: IEEE, 2007: 1373-1378.
[11] Kar R, Maheshwari V, Agarwal V, et al. Modeling of RLC Interconnect Delay for Ramp Input Using Diffusion Model Approach[C]//IEEE Symposium on Industrial Electronics and Applications. Piscataway: IEEE, 2010: 436-440.
[12] Zhang H B, Wong D F, Chao K Y, et al. A Practical Low-Power Nonregular Interconnect Design with Manufacturing for Design Approach [J]. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2012, 2(2):322-332.
[13] El-Moursy M A, Friedman E G. Wire Shaping of RLC Interconnects [J]. Integration VLSI Journal, 2007, 40(4): 461-472.
[14] University of California Berkeley. Predictive Technology Model[EB/OL]. [2012-12-30]. http://www. eas. asu. edu/~ptm/. |