关键词: 乘法器, 布什编码, 前缀加法器, 流水线

Abstract:

On the basis of the research on traditional Booth multiplier,a novel structure of pipelined Booth multiplier is proposed,which is based on radix-4 Booth encoding with Wallace tree compression structure and 64 bits Kogge-Stone prefix adder.The 32 bit×32 bit unsigned and signed rapid multiplication is realized by inserting 4-level pipeline registers in segment achieved 64 Kogge-Stone adder.The design is described in Hardware Description Language (HDL) and verified by Field Programmable Gate Array (FPGA).Then,the multiplier is synthesized by SMIC 0.18 μm CMOS process.Synthesis results show that the circuit's critical path delay is 3.6 ns,the chip area is less than 0.134 mm,and the power consumption is less than 32.69 mW.

Key words: multiplier,booth encoding,prefix adder,pipeline