关键词: 斜坡补偿, 伪PLL, 时钟同步, DCDC转换器

Abstract:

An adaptive slope compensation circuit in frequency synchronous DCDC converters is presented. Based on a pseudo phase-locked loop (PLL) structure, the slope compensation is dynamically adjusted according to the synchronized switching frequency to guarantee the stability of DCDC converters, as well as the response speed of load transient. Based on 035 μm CMOS process and Cadence software platform, simulations in the Spectre simulator verify the function of pseudo-PLL to generate adaptive slope compensation under different synchronous frequencies. Simulation results show that the proposed pseudo-PLL circuit can generate adaptive slope compensation with the frequency range 250 kHz~15 MHz, and guarantee the stability of DCDC converters.