关键词: AXI4 Stream, 数字视频信号, IP核

Abstract:

For the high speed stream data transmission between the IP core of the digital video, we design and implement an interface IP core of the digital video based on the AXI4Stream bus. The digital video signal from the external input in the ITU601 format is translated into the signal conforming with the bus protocol of AXI4Stream, and then exported to the port of the next level IP core through the main port of the IP core. The accuracy and feasibility of the proposed design have been validated by the actual hardware circuit using Xilinx ISE Design Suite 14.6.

Key words: AXI4 Stream, digital video signal, IP core