关键词: 薄型背照式面阵CCD, 复杂可编程逻辑器件, Verilog HDL

Abstract:

In order to implement the driven of area array CCD and collect realtime image,we have designed a power driven and data conversion system. Based on the extensive use of CCD, this system drives a backthinned area array CCD by the complex programmable logic device(CPLD). The CPLD control module is written in Verilog hardware description language (HDL), which is used to control the CCDs signal acquisition, signal transfer and signal transmission. According to the CCD data sheet, designing some power which the CCD needs to drive the CCD. Handling the output video signal and removing the low frequency noise such as reset noise and 1/f in filtered video signal and improving the SNR of system by the characteristics of the correlated double sample (CDS) of A/D chip. The system uses the CPLD as the core control device and makes full use the characteristics of CPLD, such as the highspeed parallel , "programmable" and the highly sensitive to the environment changing to make the speed of the signal acquisition and transmission speed be fast, and to make the output video signal be stable.

Key words: back thinned area array CCD, complex programmable logic device, Verilog HDL