基于四路ADC芯片交替采样的宽带信号采集系统设计

doi:10.16180/j.cnki.issn1007-7820.2021.09.006

摘要/Abstract

摘要：

高速高精度大带宽的信号采集系统是宽带成像雷达的重要组成部分。针对单片高精度ADC的采样率无法满足大带宽成像雷达中频直接采样的问题,文中采用多路ADC芯片交替采样的方法,在保持采样精度不变的条件下提升系统采样率。设计了一种基于4片ADC12DJ3200交替采样的宽带信号采集系统,该系统中ADC单片采样率为3.4 GS·s^-1,合成的总采样率为13.6 GS·s^-1,量化位数12 bit。测试结果表明,在440 MHz到6 140 MHz频率范围内,该系统的有效位大于7.2 bit,无杂散动态范围大于51 dB。

关键词: 模数转换器, 交替采样, 宽带雷达, 数字接收机, 采集系统, 电路设计, 宽带信号, 采样性能

Abstract:

Signal sampling system with high speed, high precision and wideband is an important part of wideband imaging radar. For the problem that the sampling rate of single high-precision ADC chip cannot meet the direct intermediate frequency sampling of wideband imaging radar, the method of multiple ADC chips time-interleaved sampling is adopted in this study, which improves the sampling rate of the system under the condition of keeping the sampling accuracy unchanged. Four ADC12DJ3200 chips with a sampling rate of 3.4 GS·s^-1 are used to design a wideband TIADC system with a total sampling rate of 13.6 GS·s^-1, and the number of quantization bits is 12 bit. The test results show that in the frequency range of 440~6 140 MHz, the effective number of bits and spurious free dynamic range of the system are more than 7.2 bit and 51 dB, respectively.

Key words: ADC, TIADC, wideband radar, digital receiver, sampling system, circuit design, wideband signal, sampling performance

中图分类号:

TN98

雷雯,栗敬雨. 基于四路ADC芯片交替采样的宽带信号采集系统设计[J]. 电子科技, 2021, 34(9): 30-35.

LEI Wen,LI Jingyu. Design of a Sampling System Based on Four-Channel ADC Chip Time-Interleaved Sampling[J]. Electronic Science and Technology, 2021, 34(9): 30-35.

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参考文献 18

[1]	刘磊. 逆合成孔径雷达二维及三维成像方法研究[D]. 西安:西安电子科技大学, 2016.
	Liu Lei. Study of two-dimensional and three-dimensional inverse synthetic aperture radar imaging methods[D]. Xi'an:Xidian University, 2016.
[2]	Zhuang Y, Xu S Y, Chen Z P, et al. ISAR imaging with sparse pulses based on compressed sensing[C]. Shanghai: Progress in Electromagnetic Research Symposium, 2016.
[3]	肖丹丹, 宿绍莹, 李涛. 基于AD9680的宽带高动态全数字雷达接收机设计[J]. 电子科技, 2015, 28(10):141-144.
	Xiao Dandan, Su Shaoying, Li Tao. Design and verification of wideband high-dynamic full digital radar receiver based on AD9680[J]. Electronic Science and Technology, 2015, 28(10):141-144.
[4]	Stambaugh J J, Lee R K, Cantrell W H. The 4 GHz bandwidth millimeter-wave radar[J]. Lincoln Laboratory Journal, 2012, 19(2):64-76.
[5]	Knott P, Perkuhn R. Non-destructive permittivity measurement of thin dielectric sheets quality conformance testing for the tracking and imaging radar TIRA[C]. Nuremberg:German Microwave Conference, 2015.
[6]	James V E, Robert L M, Weber H, et al. HUSIR signal processing[J]. Lincoln Laboratory Journal, 2014, 21(1):115-134.
[7]	Black W C, Hodges D A. Time interleaved converter arrays[J]. IEEE Journal of Solid-State Circuits, 1980, 15(6):1022-1029. doi: 10.1109/JSSC.1980.1051512
[8]	杨扩军, 田书林, 蒋俊, 等. 基于TIADC的20 GS/s高速数据采集系统[J]. 仪器仪表学报, 2014, 35(4):841-849.
	Yang Kuojun, Tian Shulin, Jiang Jun, et al. 20 GSPS high speed data acquisition system based on TIADC[J]. Chinese Journal of Scientific Instrument, 2014, 35(4):841-849.
[9]	栗敬雨, 张月, 林钱强, 陈曾平. 9.6 GS/s 10 bit宽带雷达接收机设计与实现[J]. 信号处理, 2015, 31(12):1619-1623.
	Li Jingyu, Zhang Yue, Lin Qianqiang, et al. Design and implementation of 9.6 GS/s 10 bit wideband radar receiver[J]. Journal of Signal Processing, 2015, 31(12):1619-1623.
[10]	Qiu Y, Zhou J, Liu Y, et al. An adaptive blind calibration technique for frequency response mismatches in M-channel time-interleaved ADCs[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2019, 66(4):702-706. doi: 10.1109/TCSII.8920
[11]	Qiu Y, Liu Y, Zhou J, et al. All-digital blind background calibration technique for any channel time-interleaved ADC[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2018, 65(8):2503-2514. doi: 10.1109/TCSI.2018.2794529
[12]	Reyes B, Sanchez R, Pola A, et al. Design and experimental evaluation of a time-interleaved ADC calibration algorithm for application in high-speed communication systems[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2017, 64(5):1019-1030. doi: 10.1109/TCSI.2016.2636209
[13]	Yang K J, Wei W T, Shi J L, et al. A fast TIADC calibration method for 5GS/s digital storage oscilloscope[J]. IEICE Electronics Express, 2018, 15(9):1-12.
[14]	Wang X, Li F, Jia W, et al. A 14-Bit 500-MS/s time-interleaved ADC with autocorrelation-based time skew calibration[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2019, 66(3):322-326. doi: 10.1109/TCSII.8920
[15]	Fang J. A 5-GS/s 10-b 76-mW time-interleaved SAR ADC in 28 nm CMOS[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2017, 64(7):1673-1683. doi: 10.1109/TCSI.2017.2661481
[16]	Zhao L, Jiang Z, Dong R, et al. An 8-GS/s 12-bit TIADC system with real-time broad band mismatch error correction[J]. IEEE Transactions on Nuclear Science, 2018, 65(12):2892-2900. doi: 10.1109/TNS.2018.2878875
[17]	Song J, Tian S, Hu Y. Analysis and correction of combined channel mismatch effects in frequency-interleaved ADCs[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2019, 66(2):655-668. doi: 10.1109/TCSI.2018.2869214
[18]	钟海丽, 任晓周, 任桂香, 等. 无线固定式测斜系统设计[J]. 电子设计工程, 2017, 25(12):170-172.
	Zhong Haili, Ren Xiaozhou, Ren Guixiang, et al. The design of wireless and fired inclinometer system[J]. Electronic Design Engineering, 2017, 25(12):170-172.