JPEG2000中MQ编码器的VLSI结构

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Parallel architecture in VLSI implementation of the MQ-coder for JPEG2000

CAO Bin;LI Yun-song;LIU Kai;DENG Jia-xian

(School of Telecommunication Engineering, Xidian Univ., Xi'an 710071, China)

Received:1900-01-01 Revised:1900-01-01 Online:2004-10-20 Published:2004-10-20

Abstract

Abstract: Hardware implementation of the MQ-coder for JPEG2000 standard is investigated. An efficient method for VLSI implementation described in VDHL is presented on the basis of making full use of parallel architecture. Pipe-line architecture used in this design makes several actions performed in parallel in general structure. Parallel output architecture solves the problem of generating two bytes of compressed data in one clock, and at the same time greatly improves the efficiency of producing output data. The stimulation results testify that this implementation can not only ensure the correctness, but meet the needs of the JPEG2000 coding system both in efficiency and resource occupancy.

Key words: image processing, MQ-coder, VLSI, JPEG2000, image coding

CLC Number:

TN911.81

CAO Bin;LI Yun-song;LIU Kai;DENG Jia-xian.

Parallel architecture in VLSI implementation of the MQ-coder for JPEG2000

[J].J4, 2004, 31(5): 714-718.

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Parallel architecture in VLSI implementation of the MQ-coder for JPEG2000

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