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Design of the ESD protection circuit with the gate-couple technique in CMOS technology

DU Ming;HAO Yue

  

  1. Ministry of Edu. Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi′an 710071, China
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-08-20 Published:2006-08-20

Abstract: An improved design method, the Gate-Couple technique, for the ESD protection circuit is presented for overcoming the asymmetrical turn-on of large dimension ESD protect devices. The gate-drain diffuse capacitance is used as the couple device. The capacitance couple effect can turn on the large dimension device uniformly when the ESD event occurs, and improve the performance of the ESD protection circuit. The testing of sample chips shows that the anticipated effect is achieved.

Key words: electrostatic discharge, capacitance couple, protection circuit

CLC Number: 

  • TN386