J4 ›› 2015, Vol. 42 ›› Issue (1): 56-61+206.doi: 10.3969/j.issn.1001-2400.2015.01.009

• Original Articles • Previous Articles     Next Articles

3×VDD-tolerant ESD detection circuit in a 90nm CMOS process

YANG Zhaonian;LIU Hongxia;ZHU Jia   

  1. (Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an  710071, China)
  • Received:2013-10-19 Online:2015-02-20 Published:2015-04-14
  • Contact: YANG Zhaonian E-mail:e_yangzhaonian@sina.com

Abstract:

A new low leakage 3×VDD-tolerant electrostatic discharge (ESD) detection circuit only using the low-voltage device is proposed in a 90nm 1.2V CMOS process. Gate leaky characteristics of the nanoscale MOSFET and the feedback technique are used to control the trigger MOSFET and turn on the clamp device silicon-controlled rectifier (SCR). The multi-stage stacked-transistors structure is used to sustain a high voltage stress. The proposed detection circuit can generate 38mA current to turn on the clamp device SCR under the ESD stress. Under normal 3×VDD operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 52nA under the 3×VDD bias at 25℃. Simulation result shows that the circuit can be successfully used for the 3×VDD-tolerant I/O buffer.

Key words: detection circuit, electrostatic discharge, feedback, leaky characteristic, stacked transistors

CLC Number: 

  • TN495