高吞吐量低存储量的LDPC码译码器FPGA实现

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FPGA implementation of a high-throughput memory-efficient LDPC decoder

ZHANG Gui-hua1;ZHANG Shan-xu2;LI Ying2

(1. School of Electronic Engineering, Xidian Univ., Xi′an 710071， China;
2. State Key Lab. of Integrated Service Networks, Xidian Univ., Xi′an 710071， China)

Received:1900-01-01 Revised:1900-01-01 Online:2008-06-20 Published:2008-05-30
Contact: ZHANG Gui-hua E-mail:zhangguihua1973@163.com

Abstract

Abstract: Based on the Turbo-decoding algorithm, a high-throughput memory-efficient decoder is proposed for a class of regular (r, c)-LDPC (low-density parity-check) codes. Compared to the traditional sum-product decoding algorithm, the Turbo-decoding algorithm decodes several packets in parallel, each of which is decoded by a parallel structure, resulting in faster convergence behavior and fewer memories. To decode a packet with a parallel structure, the LDC code is first divided into several super-codes. Then, each super-code is decoded by the parallel BCJR algorithm. To further simplify the inter-structure and the complexity, a modified coset algorithm is also proposed. An FPGA chip containing 15 parallel decoders for a regular (r, c)-LDPC code of length1600 has been developed based on the Altera Stratix EP1S25 FPGA device, which decodes 3 packets in parallel and can achieve a throughput of50Mbit／s with 20 decoding iterations.

Key words: LDPC code, decoder, Turbo decoding algorithm

CLC Number:

TN911.22

ZHANG Gui-hua1;ZHANG Shan-xu2;LI Ying2. FPGA implementation of a high-throughput memory-efficient LDPC decoder
[J].J4, 2008, 35(3): 427-432.

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FPGA implementation of a high-throughput memory-efficient LDPC decoder

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