一种高速低功耗的NoC时钟网络设计

doi:10.3969/j.issn.1001-2400.2013.03.017

Abstract

Abstract:

In order to achieve a high-speed low-power NoC(Network-on-chip) clock network, considering the Mesh NoC, a waterfall clock network based on the capacitively-driven low-swing transceiver in which we replace traditional MOS capacitance by metal-insulator-metal(MIM) capacitance as the driven capacitance and receiver coupling capacitance is proposed. These structures are simulated by 0.13μm CMOS technology with Spectre simulators. Results show that the proposed clock network can reach a high frequency up to 5GHz,compared with traditional networks, and this network allows up to 49％ power saving and 55％ delay reduction. At the same time, this network has a better noise suppression ability.

Key words: network-on-chip, clock network, low-power, low-swing

CLC Number:

TN402

LIU Yi;CHEN Bo;YANG Yintang;LIU Gang. High-speed low-power clock network design for NoC[J].J4, 2013, 40(3): 115-120.

References

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High-speed low-power clock network design for NoC

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