用于8位80MS/s模数转换器的增益数模单元电路

doi:10.3969/j.issn.1001-2400.2016.01.029

Abstract

Abstract:

A high speed and medium accuracy multiplying digital-to-analog converter (MDAC) circuit optimization design is presented for meeting the requirements of the 8bit, 80MS/s pipelined analog-to-digital (A/D) converter. An optimized transmission gate is adopted to improve the linearity of the MDAC circuit. In view of the high gain two-stage operational amplifier, design method in wideband operational amplifier design optimization is proposed and the settling time and power consumption of operational amplifier can be effectively decreased In addition, an improved high speed dynamic comparator is used in this design Fabricated in a 1.8V 0.18μm CMOS process, this A/D converter with the proposed MDAC circuit achieves a signal to noise and distortion ratio (SNDR) of 54.6dB and an effective number of bits (ENOB) of 7.83bit with a 35MHz input signal at the 80MHz sample rate.

Key words: multiplying digital-to-analog converter, amplifier optimization, transmission gate, dynamic comparator, pipelined analog-to-digital converter

CLC Number:

TN431.2

DONG Siwan;ZHU Zhangming;LIU Minjie;YANG Yintang. Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter[J].J4, 2016, 43(1): 162-166+172.

References

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Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter

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