Abstract: Based on the process corners analysis and equivalent Elmore delay model, a fast extreme value estimation of RLC interconnect delay induced by process variations is presented. It can be used to compute the best-case and worst-case RLC interconnect delay caused by process variations. Simulations for 68nm, 45nm, 36nm and 25nm technologies are given. Results show that the new method has the characteristics of a fast calculating speed and high accuracy, and that the proposed method is less than 7％ in error compared with the HSPICE. It can be used to analyze the delay limit of the critical path in STA.

Key words: process variations, RLC interconnect delay, process corner